{"title":"用于CMOS运算放大器的自动合成器","authors":"C. Kuo, Liang-Gee Chen, T. Parng","doi":"10.1109/EDAC.1991.206450","DOIUrl":null,"url":null,"abstract":"A design methodology with a good trade-off between design time and quality in the automatic synthesis of CMOS operational amplifiers is presented. It is based on an iterative device sizing approach in which a multivariate interpolation technique provides a way to improve the design and the SPICE simulator gives quantitative evaluation of the resultant circuit performance in each design iteration. The methodology has been implemented and proved to be very practical and promising.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An automatic synthesizer for CMOS operational amplifiers\",\"authors\":\"C. Kuo, Liang-Gee Chen, T. Parng\",\"doi\":\"10.1109/EDAC.1991.206450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A design methodology with a good trade-off between design time and quality in the automatic synthesis of CMOS operational amplifiers is presented. It is based on an iterative device sizing approach in which a multivariate interpolation technique provides a way to improve the design and the SPICE simulator gives quantitative evaluation of the resultant circuit performance in each design iteration. The methodology has been implemented and proved to be very practical and promising.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An automatic synthesizer for CMOS operational amplifiers
A design methodology with a good trade-off between design time and quality in the automatic synthesis of CMOS operational amplifiers is presented. It is based on an iterative device sizing approach in which a multivariate interpolation technique provides a way to improve the design and the SPICE simulator gives quantitative evaluation of the resultant circuit performance in each design iteration. The methodology has been implemented and proved to be very practical and promising.<>
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