A fast and efficient algorithm for determining fanout trees in large networks

Abstract

The authors present a heuristic algorithm the optimal selection of the fanout tree structures in VLSI circuit design. The algorithm minimizes area of the added buffers under the specified timing constraints. The algorithms described in the literatures solve a simpler problem of minimizing the circuit's timing without taking into account the area increase introduced by the buffers. Experimental results demonstrate that the authors' approach is very fast and efficient, particularly for large examples whose solution spaces are very large.<>