{"title":"Clock independent timing verification of level-sensitive latches","authors":"R. Tjarnstrom","doi":"10.1109/EDAC.1991.206406","DOIUrl":null,"url":null,"abstract":"The author presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"261 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206406","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The author presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected.<>