Clock independent timing verification of level-sensitive latches

R. Tjarnstrom
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引用次数: 4

Abstract

The author presents a method to automatically handle level-sensitive latches in timing analysis/verification. Timing specifications, including delays and timing constraints, are automatically generated for the cells in the design. The generated timing specifications are independent of clocking strategy, since clock and data are treated equally. Conditional constraints and paths are used to capture the transparent property of latches. The constraint rules are based on electrical/physical laws instead of assumptions about design styles. Timing errors due to clock skew and improper design are detected.<>
电平敏感锁存器的时钟独立定时验证
作者提出了一种在时序分析/验证中自动处理电平敏感锁存的方法。时序规范,包括延迟和时序约束,将自动为设计中的单元生成。生成的时序规范独立于时钟策略,因为时钟和数据被平等对待。条件约束和路径用于捕获锁存器的透明属性。约束规则是基于电子/物理定律,而不是关于设计风格的假设。检测到由于时钟倾斜和设计不当导致的定时错误。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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