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Proceedings of the European Conference on Design Automation.最新文献

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Translating system specifications to VHDL 将系统规格转换为VHDL
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206432
Sanjiv Narayan, F. Vahid, D. Gajski
{"title":"Translating system specifications to VHDL","authors":"Sanjiv Narayan, F. Vahid, D. Gajski","doi":"10.1109/EDAC.1991.206432","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206432","url":null,"abstract":"Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
HITEC: a test generation package for sequential circuits 用于顺序电路的测试生成包
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206393
T.M. Niermann, J. Patel
{"title":"HITEC: a test generation package for sequential circuits","authors":"T.M. Niermann, J. Patel","doi":"10.1109/EDAC.1991.206393","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206393","url":null,"abstract":"Presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state. Several new techniques are introduced to improve the performance of test generation. A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specification of state variables which can sometimes result when using a standard PODEM algorithm. A technique to use the state knowledge of previously generated vectors for state justification, without the memory overhead of a state transition diagram is presented. For faults that were aborted during the standard test generation phase, knowledge that was gained about fault propagation, by the fault simulator, is used. These techniques, when used together, produce the best published results for the ISCAS89, sequential benchmark circuits.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124620022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 695
Mickey: a macro cell global router 米奇:一个宏单元全局路由器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206400
Dahe Chen, C. Sechen
{"title":"Mickey: a macro cell global router","authors":"Dahe Chen, C. Sechen","doi":"10.1109/EDAC.1991.206400","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206400","url":null,"abstract":"The authors present a new graph-based macro cell global router. The placement of the macro cells need not have the slicing structure and the macro cells may have any rectilinear shape. A key contribution is a new algorithm which efficiently generates M shortest routes for every net. The global router then selects one route for each net while seeking to avoid the net routing-order dependence problem. Mickey has two different objective functions, making it applicable to different design styles. It can be used to either minimize the chip area or to minimize the total wire length under channel capacity constraints. Test results on industrial circuits show that Mickey outperforms existing approaches.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121061902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Efficient shape curve construction in floorplan design 平面图设计中高效的形状曲线构造
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206424
Ting-Chi Wang, D. F. Wong
{"title":"Efficient shape curve construction in floorplan design","authors":"Ting-Chi Wang, D. F. Wong","doi":"10.1109/EDAC.1991.206424","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206424","url":null,"abstract":"The authors present an efficient algorithm to construct shape curves for VLSI floorplans. Their algorithm is based on extensions of a tree-restructuring technique and a curve-adding technique. They assume each module in the floorplan has an infinite number of non-redundant implementations specified (or approximated) by a piecewise linear decreasing shape curve. Their algorithm constructs a shape curve that contains all non-redundant implementations of the floorplan. Experimental results indicate that the algorithm performs well.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132583090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the selection of a partial scan path with respect to target faults 针对目标故障选择局部扫描路径
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206394
Harald Gundlach, Bernd K. Koch, K. Müller-Glaser
{"title":"On the selection of a partial scan path with respect to target faults","authors":"Harald Gundlach, Bernd K. Koch, K. Müller-Glaser","doi":"10.1109/EDAC.1991.206394","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206394","url":null,"abstract":"Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path, existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132593055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
High level synthesis: a data path partitioning method dedicated to speed enhancement 高级综合:一种致力于提高速度的数据路径划分方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206374
F. Monteiro, B. Rouzeyre, G. Sagnes
{"title":"High level synthesis: a data path partitioning method dedicated to speed enhancement","authors":"F. Monteiro, B. Rouzeyre, G. Sagnes","doi":"10.1109/EDAC.1991.206374","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206374","url":null,"abstract":"In the field of high level synthesis, a speed improvement of structural designs can be obtained by partitioning the physical data path of the behavioral compilers outcome. This speed improvement is achieved by increasing the number of operations treated simultaneously without appreciable overhead in the silicon area. The authors present a partitioning method based on bus splitting. This method makes use of hierarchical clustering and a description of all the measures needed for partitioning is given.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On probabilistic switch-level simulation for asynchronous circuits
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206420
S. Rajgopal, A. Tyagi
{"title":"On probabilistic switch-level simulation for asynchronous circuits","authors":"S. Rajgopal, A. Tyagi","doi":"10.1109/EDAC.1991.206420","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206420","url":null,"abstract":"The delay information useful in asynchronous circuits is not the same as in synchronous circuits. Rather than using the worst case delay, usually computed by a critical path analysis, the average case delay over a set of input assignments is a more relevant parameter for an asynchronous system. The authors present a novel, probability-propagation based algorithm to comput the average case switch-level delays. They discuss an implementation of this algorithm which is built on top of RNL, an event-driven switch-level simulator. This implementation takes the same order of time that RNL takes to simulate for one input assignment for determining the average case delays.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131081144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Formal sizing rules of CMOS circuits CMOS电路的正式尺寸规则
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206368
D. Auvergne, N. Azémard, V. Bonzom, D. Deschacht, M. Robert
{"title":"Formal sizing rules of CMOS circuits","authors":"D. Auvergne, N. Azémard, V. Bonzom, D. Deschacht, M. Robert","doi":"10.1109/EDAC.1991.206368","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206368","url":null,"abstract":"Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130033370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A distributed engineering database management system for IC design 集成电路设计分布式工程数据库管理系统
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206354
W. Cao, Y. Lien, Yuane Qiu, L. Shao
{"title":"A distributed engineering database management system for IC design","authors":"W. Cao, Y. Lien, Yuane Qiu, L. Shao","doi":"10.1109/EDAC.1991.206354","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206354","url":null,"abstract":"Describes a distributed engineering database subsystem (DDB) which is an integral part of the framework in the PANDA IC-CAD system. DDB provides a simple but efficient method for organizing the IC design data in a distributed environment. With version management and concurrency control services, DDB supports the iterative, tentative and collaborative nature of the design process. A database schema based on the concept of object and how it is used as the foundation for tool integration are also discussed.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117305991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Iterative compaction: an improved approach to graph and circuit bisection 迭代压缩:图和电路平分的改进方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206462
J. Haralambides, F. Makedon
{"title":"Iterative compaction: an improved approach to graph and circuit bisection","authors":"J. Haralambides, F. Makedon","doi":"10.1109/EDAC.1991.206462","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206462","url":null,"abstract":"Given a graph G=(V,E), graph bisection is the problem of finding a partition of the vertex set V in two equal-sized subsets V/sub 1/ and V/sub 2/ so that the number of edges between them is minimized. This problem has important applications in circuit partitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. The authors introduce a new heuristic approach, called iterative compaction (IC), which employees a node degree based matching and iterative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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