Circuit partitioning into small sets: a tool to support testing with further applications

Abstract

The authors consider a general partitioning problem, namely how to partition the elements of a circuit into sets of size less than a small constant, so that the number of nets which connect elements in different sets is minimized. One application is in the design for testability of VLSI chips and printed circuit boards. The authors consider two different versions of a bottom-up iterative approach. In the first version they present an efficient heuristic. In an alternative version, the heuristic is used as a subroutine to an approximation (provably good) algorithm, resulting in comparably good solutions. The authors compare both approaches with the familiar top-down approach which uses a well known bisection heuristic as a subroutine. These solutions outperform the top-down partitioning approach.<>