{"title":"MACHETE: synthesis of sequential machines for easy testability","authors":"B. Vinnakota, N. Jha","doi":"10.1109/EDAC.1991.206410","DOIUrl":null,"url":null,"abstract":"Test generation for sequential machines is known to be computationally expensive. The authors present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Test generation for sequential machines is known to be computationally expensive. The authors present a scheme, called MACHETE (MACHines for Easy TEstability), for synthesizing easily testable architectures for sequential machines by adding some state transitions and their associated output vectors to the state transition table. This is done to make the internal states of the machine easily controllable as well as observable. This can enable us to obtain a high fault coverage in reasonable amounts of CPU time.<>
众所周知,顺序机器的测试生成在计算上是昂贵的。作者提出了一种名为MACHETE (MACHines for Easy TEstability)的方案,通过向状态转换表中添加一些状态转换及其相关的输出向量,来合成顺序机器的易于测试的体系结构。这样做是为了使机器的内部状态易于控制和观察。这可以使我们在合理的CPU时间内获得较高的故障覆盖率。