CMOS功能单元的延迟估计

J. Madsen
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引用次数: 0

摘要

提出了一种新的用于CMOS功能单元时延估计的RC树网络模型。该模型能够反映单元内的拓扑变化,这在进行性能驱动的布局合成时特别有趣。此外,还提出了一套算法,利用所提出的延迟模型对任意CMOS功能单元进行最坏情况分析。模型和算法都作为细胞编译器(CELLO)的一部分在实验硅编译器环境中实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Delay estimation for CMOS functional cells
Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.<>
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