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Proceedings of the European Conference on Design Automation.最新文献

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An approach to design flow management in CAD frameworks (for VLSI) CAD框架中的设计流程管理方法(适用于VLSI)
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206355
M. Mehendale
{"title":"An approach to design flow management in CAD frameworks (for VLSI)","authors":"M. Mehendale","doi":"10.1109/EDAC.1991.206355","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206355","url":null,"abstract":"The approach described is based on a parallel that can be established between the design flow and the logic design domains. The paper describes how these mappings can be used to apply the existing techniques and algorithms of the logic design process to the problem of design flow management, thus providing solutions for design flow specification, representation, synthesis, flow data management and flow execution, in CAD frameworks. A 'design flow' view in EDIF has been proposed. It can be used as a standard interchange format for migrating flows across frameworks.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128913867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Area and performance optimizations in path-based scheduling 基于路径调度的区域和性能优化
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206413
R. Bergamaschi, R. Camposano, M. Payer
{"title":"Area and performance optimizations in path-based scheduling","authors":"R. Bergamaschi, R. Camposano, M. Payer","doi":"10.1109/EDAC.1991.206413","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206413","url":null,"abstract":"The authors describe the area and performance optimizations implemented in the As-Fast-As-Possible (AFAP) scheduling algorithm. The AFAP scheduling algorithm is a path-based technique that finds the minimum number of control steps for all possible sequences of operations in the control-flow graph, under given constraints. Area requirements for functional units, such as their number and type, are translated into constraints which are then met exactly. The number of registers is also minimized. The performance optimizations included in this paper are concerned mainly with the scheduling of loops.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"4 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121015476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
CASCH-a scheduling algorithm for 'high level'-synthesis cash -一种用于“高级”合成的调度算法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206414
P. Gutberlet, Heinrich Krämer, W. Rosenstiel
{"title":"CASCH-a scheduling algorithm for 'high level'-synthesis","authors":"P. Gutberlet, Heinrich Krämer, W. Rosenstiel","doi":"10.1109/EDAC.1991.206414","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206414","url":null,"abstract":"It is the goal of the recently developed and herewith presented scheduling algorithm to optimize the timing behaviour within automated circuit synthesis. The algorithm is a part of the CADDY-synthesis-system (CAddy SCHeduling). The basis is a list scheduling algorithm which is controlled by a heuristic rating function. The allocated resources can be modelled in a flexible and detailed manner in order to specify component types for several different operations as well as different component types for the same operation. It is a special feature of this scheduling algorithm that the assignment of operations to component types is decided during the scheduling.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123312532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An algorithm for improving optimal placement for river-routing 一种改进河道优化布局的算法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206396
S. Healey
{"title":"An algorithm for improving optimal placement for river-routing","authors":"S. Healey","doi":"10.1109/EDAC.1991.206396","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206396","url":null,"abstract":"Describes a linear-time, terminal-position assignment algorithm that can be used in conjunction with the optimal-placement-for-river-routing algorithm to eliminate, or greatly reduce, the routing area between cells within a module. The terminal-position algorithm that is described, may be used to optimize the positions of the interconnections between the interior rows and columns of cells within a module for custom module generation. The method uses river routing within the cells to virtually eliminate routing channels between the cell rows and columns while producing little or no increase in cell area. Use of this pin assignment algorithm for optimizing the interconnections between custom-synthesized cells provides a significant improvement in area usage.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117301058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Partitioning a network into n pieces with a time-efficient net cost function 使用高效的净代价函数将网络划分为n个部分
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206385
P. Stravers
{"title":"Partitioning a network into n pieces with a time-efficient net cost function","authors":"P. Stravers","doi":"10.1109/EDAC.1991.206385","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206385","url":null,"abstract":"Discusses the generalization of the Fiduccia-Mattheyses linear time bi-partitioning algorithm to a linear-time n-partitioning algorithm. It uses a new heuristic cost function to evaluate the cost of arbitrarily large spanning trees in O(log n) time. Practical experiments show good results.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131494524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Experiments with autonomous test of PLAs pla自主测试实验
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206458
E. Aas, Gunnar Nystu
{"title":"Experiments with autonomous test of PLAs","authors":"E. Aas, Gunnar Nystu","doi":"10.1109/EDAC.1991.206458","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206458","url":null,"abstract":"An architecture for BIST of PLAs is presented, together with a testability analysis tool to assert test quality. The functionality of the PLA itself is utilized for stimuli generation. Experiments assert that the test patterns generated can be considered as random patterns with equal 1 and 0 probability of each input. Test quality is measured based upon computed fault detectability and estimated fault coverage at a desired confidence level. A set of 53 PLA benchmark circuits from Berkeley is used to demonstrate the features of the method. It is found that 37 of 53 PLAs are random testable to 99% fault coverage with less than 100000 patterns.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114651364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A hierarchical approach to timing verification in CMOS VLSI design CMOS VLSI设计中时序验证的分层方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206405
H. G. Yang, D. Holburn
{"title":"A hierarchical approach to timing verification in CMOS VLSI design","authors":"H. G. Yang, D. Holburn","doi":"10.1109/EDAC.1991.206405","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206405","url":null,"abstract":"The author describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, the authors discuss the impact on design strategy of the hierarchical delay model presented in this paper.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116927530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Restructuring VLSI layout representations for efficiency 重组VLSI布局表示以提高效率
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206371
R. Nair, V. Chickermane, R. Chamberlain
{"title":"Restructuring VLSI layout representations for efficiency","authors":"R. Nair, V. Chickermane, R. Chamberlain","doi":"10.1109/EDAC.1991.206371","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206371","url":null,"abstract":"VLSI mask layouts usually have a hierarchical representation which serves to record the structure of the design while saving storage space. It is often convenient to work directly on such a representation for performing some operations. However for many other operations it is preferable to work on the flattened representation of the circuit. The authors look at the unnesting operation on layouts to demonstrate that simple transformations of one hierarchy to an equivalent one help tremendously in improving the performance of typical operations on hierarchical layout representations, while not requiring as much memory as flattened representations.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130300820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A proposed hardware fault simulation engine 提出了一种硬件故障仿真引擎
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206472
Daniel Cock, A. Carpenter
{"title":"A proposed hardware fault simulation engine","authors":"Daniel Cock, A. Carpenter","doi":"10.1109/EDAC.1991.206472","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206472","url":null,"abstract":"Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modifications necessary to make MANSE capable of fault simulation are considered.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125299174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DONALD: a workbench for interactive design space exploration and sizing of analog circuits DONALD:一个用于交互设计空间探索和模拟电路尺寸的工作台
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206451
K. Swings, W. Sansen
{"title":"DONALD: a workbench for interactive design space exploration and sizing of analog circuits","authors":"K. Swings, W. Sansen","doi":"10.1109/EDAC.1991.206451","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206451","url":null,"abstract":"Presents the program DONALD. DONALD constitutes a new approach to the use of numerical computation in circuit sizing. The program is able to numerically invert an analytic design model of an analog circuit in any arbitrary direction. It is therefore possible to answer with DONALD both design questions: analysis questions, as well as technology questions. To accomplish this, the program uses a new, heuristic algorithm for detection of minimal clusternodes in bipartite graphs. A graphical, mouse oriented user interface allows the user to make strategic and optimum moves through a circuit's design space.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122572612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
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