A proposed hardware fault simulation engine

Abstract

Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modifications necessary to make MANSE capable of fault simulation are considered.<>