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Proceedings of the European Conference on Design Automation.最新文献

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Detection of PLA multiple crosspoint faults 聚乳酸多交点故障检测
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206364
M. Ambanelli, M. Favalli, P. Olivo, B. Riccò
{"title":"Detection of PLA multiple crosspoint faults","authors":"M. Ambanelli, M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/EDAC.1991.206364","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206364","url":null,"abstract":"An original approach to fault simulation of crosspoint faults in PLAs that goes beyond the normal assumption of single defects is presented: such a method, using concepts derived from critical path backtracing, makes use of the minimum set of information needed for exact, complete analysis without treating each fault individually. Experimental results are also presented to show the importance of multiple faults in common PLAs as well as to discuss the simulator performance.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114945983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Model-based fault diagnosis of sequential circuits and its acceleration 基于模型的顺序电路故障诊断及其加速
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206395
B. Rogel-Favila, A. Wakeling, P. Cheung
{"title":"Model-based fault diagnosis of sequential circuits and its acceleration","authors":"B. Rogel-Favila, A. Wakeling, P. Cheung","doi":"10.1109/EDAC.1991.206395","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206395","url":null,"abstract":"Describes an algorithm for the location of faulty components in digital circuits using the model-based approach to circuit fault diagnosis. The model-based approach is first extended to apply to synchronous sequential circuits. Acceleration strategies that exploit domain knowledge particular to digital circuits are then proposed. The effect of these acceleration strategies is a drastic reduction in the execution time of the diagnosis procedure. The effectiveness and performance of the diagnosis algorithm are illustrated through an example for which encouraging results are obtained.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132002502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Formal methods for silicon compilation 用于硅编译的形式化方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206433
T. Kalker
{"title":"Formal methods for silicon compilation","authors":"T. Kalker","doi":"10.1109/EDAC.1991.206433","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206433","url":null,"abstract":"At the Philips Research Laboratories there is a large research effort on silicon compilation for DSP applications. The PIRAMID system is a prototype compiler which is capable of going from specification to layout within a few hours. The input language for PIRAMID has an applicative nature and is called SILAGE. In order to reduce the number of mistakes made during specification a good formal semantics of SILAGE is an absolute necessity. A study into the feasibility of denoting the formal semantics of SILAGE in the mathematical notation of higher order logic revealed several weak points of SILAGE. This paper shows that using mathematical methods one can define a better (with respect to specification/verification purposes) version of SILAGE (SILAGE+) without really adding to the complexity of the PIRAMID compiler.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"96 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132297906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Concurrent min-max simulation 并发最小-最大仿真
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206469
E. Ulrich, K. Panetta, S. Demba, R. Razdan
{"title":"Concurrent min-max simulation","authors":"E. Ulrich, K. Panetta, S. Demba, R. Razdan","doi":"10.1109/EDAC.1991.206469","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206469","url":null,"abstract":"Parametric process variations, which are inherent in the manufacture of complex digital circuits, can cause variations in the timing characteristics of a digital device. These device timing variations can cause catastrophic failures to the intended logical operation of the whole design. Min-max timing simulation is simulation technique which is well suited to verify that a given design functions correctly, even under the influence of parametric process variations. Unfortunately, in the past, min-max timing simulation has been very expensive in simulation CPU time and in the amount of memory consumed. The authors present a technique, concurrent min-max simulation (CMMS), which employs the techniques developed in concurrent fault simulation, to elegantly solve the min-max timing simulation problem.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A performance analysis tool for performance-driven micro-cell generation 性能驱动微电池生成的性能分析工具
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206474
R. Llopis, R.J.H. Koopman, H. Kerkhoff, J. Braat
{"title":"A performance analysis tool for performance-driven micro-cell generation","authors":"R. Llopis, R.J.H. Koopman, H. Kerkhoff, J. Braat","doi":"10.1109/EDAC.1991.206474","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206474","url":null,"abstract":"A new method is presented to determine the power dissipation and propagation-delay time of small logical blocks (micro-cells). This method is a combination of the RC-tree and the macro modeling methods. It is a fast and accurate method, three orders of magnitude faster that SPICE, while the maximal error is ten percent. This method can be used in a performance-driven micro-cell generator for a sea-of-gates environment.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133296965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Module synthesis for finite state machines 有限状态机的模块综合
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206475
A. Kuehlmann, Y. Manoli
{"title":"Module synthesis for finite state machines","authors":"A. Kuehlmann, Y. Manoli","doi":"10.1109/EDAC.1991.206475","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206475","url":null,"abstract":"The authors present a new layout style for automatic synthesis of finite state machines which is suitable for full custom as well as sea-of-gate layouts. It is based on a combined use of slice techniques, which result in a compact layout and a matrix layout style to ensure the flexibility of this approach. For the layout optimization, multiple row folding has to be performed, for which a genetic optimization algorithm is presented. Some experimental results are given.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Incremental switch-level simulation with zero/integer-delay 零/整延迟增量开关级仿真
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206419
L. G. Jones
{"title":"Incremental switch-level simulation with zero/integer-delay","authors":"L. G. Jones","doi":"10.1109/EDAC.1991.206419","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206419","url":null,"abstract":"The authors present the methods used in the implementation of an incremental zero/integer-delay switch-level logic simulation for MOS circuits based on the MOSSIM II switch-level model. Zero-delay timing reduces spurious re-evaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing, a generalization of unit-delay methods, provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a fully-integrated capture-compile-simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116775200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new decomposition method for multilevel circuit design 一种新的多电平电路设计分解方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206428
D. Bochmann, F. Dresig, B. Steinbach
{"title":"A new decomposition method for multilevel circuit design","authors":"D. Bochmann, F. Dresig, B. Steinbach","doi":"10.1109/EDAC.1991.206428","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206428","url":null,"abstract":"Presents a new methodology for the decomposition of Boolean functions, which is exclusively based on the utilization of function properties. The main point in this connection is the 'groupability' of Boolean functions. The analysis of uncompletely specified functions is carried out by means of Boolean differential equations. Examples demonstrate the efficiency of the automatic implementation.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124987089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Structure based methods for parallel pattern fault simulation in combinational circuits 基于结构的组合电路并联方向图故障仿真方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206457
B. Becker, R. Hahn, Rolf Krieger, U. Sparmann
{"title":"Structure based methods for parallel pattern fault simulation in combinational circuits","authors":"B. Becker, R. Hahn, Rolf Krieger, U. Sparmann","doi":"10.1109/EDAC.1991.206457","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206457","url":null,"abstract":"The authors present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fan-out stems for which the fault simulation has to be performed and on the other hand at a reduction of gate evaluations during the fault simulation. Of course, all methods support the use of parallel pattern evaluation.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Affine transformations for multi-dimensional signal processing on ASIC regular arrays 基于ASIC规则阵列的多维信号处理仿射变换
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206443
J. Rosseel, Michaël F. X. B. van Swaaij, F. Catthoor, H. Man
{"title":"Affine transformations for multi-dimensional signal processing on ASIC regular arrays","authors":"J. Rosseel, Michaël F. X. B. van Swaaij, F. Catthoor, H. Man","doi":"10.1109/EDAC.1991.206443","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206443","url":null,"abstract":"The problems involved with high-level synthesis of ASIC regular arrays for multi-dimensional signal processing applications will be outlined. The goal is to map nonuniform recurrence equations on regular arrays with realistic constraints on area, throughput and I/O bandwidth. Algorithms for multi-dimensional signal processing often involve a large number of indices. In this paper, novel techniques are presented that are needed to map these multi-index algorithms onto regular arrays with limited dimension.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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