Concurrent min-max simulation

Abstract

Parametric process variations, which are inherent in the manufacture of complex digital circuits, can cause variations in the timing characteristics of a digital device. These device timing variations can cause catastrophic failures to the intended logical operation of the whole design. Min-max timing simulation is simulation technique which is well suited to verify that a given design functions correctly, even under the influence of parametric process variations. Unfortunately, in the past, min-max timing simulation has been very expensive in simulation CPU time and in the amount of memory consumed. The authors present a technique, concurrent min-max simulation (CMMS), which employs the techniques developed in concurrent fault simulation, to elegantly solve the min-max timing simulation problem.<>