Incremental switch-level simulation with zero/integer-delay

Abstract

The authors present the methods used in the implementation of an incremental zero/integer-delay switch-level logic simulation for MOS circuits based on the MOSSIM II switch-level model. Zero-delay timing reduces spurious re-evaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing, a generalization of unit-delay methods, provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a fully-integrated capture-compile-simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit.<>