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Proceedings of the European Conference on Design Automation.最新文献

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GENVIEW: a portable source-level debugger for macrocell generators GENVIEW:用于宏单元生成器的便携式源代码级调试器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206436
A. Compan, A. Greiner, F. Pêcheux, F. Pétrot
{"title":"GENVIEW: a portable source-level debugger for macrocell generators","authors":"A. Compan, A. Greiner, F. Pêcheux, F. Pétrot","doi":"10.1109/EDAC.1991.206436","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206436","url":null,"abstract":"An effective layout design method for VLSI macrocell is presented. The method describes a way to write, to test and to validate efficient full-custom generators and tilers. First, after a brief overview of the design methodology of tilers, the GENLIB C-library of procedural design functions is described. Second, GENVIEW, a portable and graphic layout debugger for the interactive testing of generators, is detailed.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"124 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113991514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Functional abstraction of logic gates for switch-level simulation 开关级仿真逻辑门的功能抽象
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206418
D. Blaauw, D. Saab, P. Banerjee, J. Abraham
{"title":"Functional abstraction of logic gates for switch-level simulation","authors":"D. Blaauw, D. Saab, P. Banerjee, J. Abraham","doi":"10.1109/EDAC.1991.206418","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206418","url":null,"abstract":"Switch-level simulation has become a common means accurate modeling of MOS circuit behavior. In this paper, the authors propose a new method for detecting logic gate implementation and accurately modeling their switch-level behavior. The functional abstraction replaces logic gate implementation in the switch-level description with an accurate high-level model which incorporates all relevant switch-level phenomena. The switch-level accuracy of the simulation is, therefore, preserved. However, since the gate implementations are modeled at a higher, more abstract level, the simulation speed is greatly increased. The functional abstraction is automatic and completely transparent to the user. Detection of a gate is determined by expressing the logic function of a transistor network in the sum-of-product notation and is not limited to a specific design style. The proposed algorithms have been implemented and tested on several large circuits, including a complete microprocessor. For this processor, 85% of all transistors were substituted with high-level models. A significant decrease in simulation time and storage requirement occurred for these circuits when gate abstraction was performed.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An approach to the analysis and test of crosstalk faults in digital VLSI circuits 数字VLSI电路串扰故障的分析与测试方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206363
A. Rubio, N. Itazaki, Xiaole Xu, K. Kinoshita
{"title":"An approach to the analysis and test of crosstalk faults in digital VLSI circuits","authors":"A. Rubio, N. Itazaki, Xiaole Xu, K. Kinoshita","doi":"10.1109/EDAC.1991.206363","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206363","url":null,"abstract":"The continuous reduction of the device size in integrated circuits and the increasing of the switching rate cause parasitic capacitances between conducting layers which might become dominant enough to provoke logic errors in the circuits. So, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this sort of faults. This paper presents a logic fault characterization of these faults, a logic level circuit fault model, a crosstalk fault list generator working at layout level and a test pattern generation procedure for crosstalk type faults.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Resolution-based correctness proofs of synchronous circuits 同步电路的基于分辨率的正确性证明
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206349
P. Camurati, T. Margaria, P. Prinetto
{"title":"Resolution-based correctness proofs of synchronous circuits","authors":"P. Camurati, T. Margaria, P. Prinetto","doi":"10.1109/EDAC.1991.206349","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206349","url":null,"abstract":"First-order theorem provers like OTTER satisfy the vital need for versatility and efficiency in formal verification of correctness. This paper deals with experiences in applying OTTER to synchronous circuits. Synchronous circuits are first modeled, then proved correct by means of demodulation- and hyperresolution-based methodologies. Experimental examples are discussed, results are reported and a first comparison is drawn with other proof styles.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116975363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A hardware design system based on object-oriented principles 基于面向对象原则的硬件设计系统
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206447
A. V. D. Hoeven, E. Deprettere, P. V. Prooijen, P. Dewilde
{"title":"A hardware design system based on object-oriented principles","authors":"A. V. D. Hoeven, E. Deprettere, P. V. Prooijen, P. Dewilde","doi":"10.1109/EDAC.1991.206447","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206447","url":null,"abstract":"Most hardware description languages and their environments are either based on imperative language concepts or on functional language concepts. The authors propose a hardware specification and simulation environment based on object-oriented principles. Object-oriented concepts such as classes, objects, inheritance and abstraction are considered in a design environment with the HiFi hardware design model as its underlying basis. The model uses single token Petri nets and applicative state transitions to describe the functionality and data flow of a VLSI network.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116190085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization techniques for multiple output function synthesis 多输出函数合成的优化技术
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206467
G. Buonanno, D. Sciuto, R. Stefanelli
{"title":"Optimization techniques for multiple output function synthesis","authors":"G. Buonanno, D. Sciuto, R. Stefanelli","doi":"10.1109/EDAC.1991.206467","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206467","url":null,"abstract":"Design of multiple outputs CMOS combinational gates is considered. Two techniques for the minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. A branch and bound algorithm to be used for complex gate synthesis is presented. Design examples are also provided. It is shown that the two techniques can be combined together, if necessary, to obtain further area reductions.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125777088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Synthesis of multi-level logic with one symbolic input 一个符号输入的多级逻辑综合
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206360
F. Buijs, Thomas Lengauer
{"title":"Synthesis of multi-level logic with one symbolic input","authors":"F. Buijs, Thomas Lengauer","doi":"10.1109/EDAC.1991.206360","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206360","url":null,"abstract":"Presents algorithms that perform multi-level logic synthesis on logic with one symbolic input. This method contrasts to existing approaches that encode a symbolic input before logic synthesis. These approaches determine the encoding based on heuristic estimates. The present algorithms, which perform logic synthesis directly on the logic with the symbolic input, enable one to encode the symbolic input after logic synthesis. Since the authors determine the encoding based on the result of the multi-level logic synthesis, instead of heuristic estimates, they obtain better encodings and hence smaller logic. Experiments on a number of benchmarks show improvements up to 49%.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124437689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Test scheduling and controller synthesis in the CADDY-system caddy系统中的测试调度与控制器综合
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206408
M. Rudolph, M. Neher, W. Rosenstiel
{"title":"Test scheduling and controller synthesis in the CADDY-system","authors":"M. Rudolph, M. Neher, W. Rosenstiel","doi":"10.1109/EDAC.1991.206408","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206408","url":null,"abstract":"In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new approach to layout of custom analog cells 一种自定义模拟单元布局的新方法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206452
L. Donzelle, P. Dubois
{"title":"A new approach to layout of custom analog cells","authors":"L. Donzelle, P. Dubois","doi":"10.1109/EDAC.1991.206452","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206452","url":null,"abstract":"A new layout system for analog cells is presented. Unlike most other systems, the problem of interaction is addressed: the goal is to enable an analog expert to achieve the layout of common analog cells, in less than half a day, the final result being as good as a totally handcrafted layout. The system is divided into two main parts: first, the primitives which are necessary to generate the layout of analog cells (generation of devices, associations and symmetries of basic elements, interactive routing); second, an easy to use graphic environment, which provides enough interaction in the manipulation of basic structures to enable the designer to reach the layout he desires. Many real cells have been laid out using this tool. Some final results on silicon are reported.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131690405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Decomposing data machines 分解数据机
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206429
W. Wolf
{"title":"Decomposing data machines","authors":"W. Wolf","doi":"10.1109/EDAC.1991.206429","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206429","url":null,"abstract":"Describes a new FSM decomposition algorithm which extracts a data register from a given FSM. The algorithm is a generalization of the standard minimization algorithm-it selects output values which, when stored in a separate data register, will make additional states in the control machine equivalent. Experimental results show that the algorithm is both effective and fast.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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