{"title":"caddy系统中的测试调度与控制器综合","authors":"M. Rudolph, M. Neher, W. Rosenstiel","doi":"10.1109/EDAC.1991.206408","DOIUrl":null,"url":null,"abstract":"In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Test scheduling and controller synthesis in the CADDY-system\",\"authors\":\"M. Rudolph, M. Neher, W. Rosenstiel\",\"doi\":\"10.1109/EDAC.1991.206408\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206408\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206408","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test scheduling and controller synthesis in the CADDY-system
In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.<>
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