GENVIEW: a portable source-level debugger for macrocell generators

Abstract

An effective layout design method for VLSI macrocell is presented. The method describes a way to write, to test and to validate efficient full-custom generators and tilers. First, after a brief overview of the design methodology of tilers, the GENLIB C-library of procedural design functions is described. Second, GENVIEW, a portable and graphic layout debugger for the interactive testing of generators, is detailed.<>