基于无序码编码的自检PLA自动生成工具

K. Torki, M. Nicolaidis, A. O. Fernandes
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引用次数: 4

摘要

自检电路通过硬件冗余确保并发错误检测。自检电路的一个重要缺点是设计时间的显著增加。需要特定的CAD工具来处理这个缺点。在本文中,作者提出了一种允许自动生成自检pla的工具。然后,他们通过将一组PLA基准转换为自检PLA并给出有关所需面积开销的统计数据来验证该工具
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A self-checking PLA automatic generator tool based on unordered codes encoding
Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is the fact that they involve a significant increasing of the design time. Specific CAD tools are needed in order to cope with this drawback. In this paper the authors present a tool allowing automatic generation of self-checking PLAs. Then they validate this tool by transforming a set of PLA benchmarks into self-checking PLAs and give statistics concerning the required area overhead.<>
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