VLSI并行开关级仿真

R. Mueller-Thuns, D. Saab, J. Abraham
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引用次数: 5

摘要

开关级仿真广泛应用于超大规模集成(VLSI) MOS电路的设计验证过程中。在本文中,作者提出了通过将开关级仿真映射到通用并行计算机上来加速开关级仿真的方法。他们的目标机器是中粒度多处理器(共享内存或消息传递机),他们只考虑模型并行计算,其中要模拟的设计模型在处理器之间进行分区。介绍了有效的电路划分策略以及相应的仿真算法。在作者的方法中,他们尝试最小化处理器之间的同步总数,并确保可移植性和可伸缩性。实现了预处理器和模拟器,并在一组基准测试中获得了良好的性能。强调了以分布式方式评估电路中强连接组件的处理器之间的紧密耦合问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Parallel switch-level simulation for VLSI
Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.<>
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