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Proceedings of the European Conference on Design Automation.最新文献

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TATOO: an industrial timing analyzer with false path elimination and test pattern generation TATOO:一个工业时序分析仪与假路径消除和测试模式生成
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206403
J. Benkoski, Ronald B. Stewart
{"title":"TATOO: an industrial timing analyzer with false path elimination and test pattern generation","authors":"J. Benkoski, Ronald B. Stewart","doi":"10.1109/EDAC.1991.206403","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206403","url":null,"abstract":"TATOO is an industrial interactive timing analysis system evolved from recently developed false path elimination algorithms. These have been extended to perform more complex searches that facilitate the rapid survey of a network. An automatic test pattern generation mechanism which exercises the statically sensitizable paths has been developed. This forms a direct link to an electrical simulator. The critical path through a network of hundreds of gates is found, the test pattern generated, the critical path simulated, and the resulting waveforms displayed in less than two minutes.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133773462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design by similarity using transaction modeling and statistical techniques 使用事务建模和统计技术进行相似性设计
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206448
A. Kabbaj, E. Cerny, M. Dagenais, François Bouthillier
{"title":"Design by similarity using transaction modeling and statistical techniques","authors":"A. Kabbaj, E. Cerny, M. Dagenais, François Bouthillier","doi":"10.1109/EDAC.1991.206448","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206448","url":null,"abstract":"Presents a new VLSI design management system. Unlike existing systems it models and stores not only the design data but also a description of the design process itself. This information is accumulated and used to present the designer with alternative design methodologies and to suggest the most promising one, based on previous designs. Experimental results on 22 simple designs indicate that the system selected the most appropriate methodology in 81% of the cases.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hybrid compiled/interpreted simulation of MOS circuits MOS电路的混合编译/解释仿真
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206470
L. McMurchie, Craig Anderson, G. Borriello
{"title":"Hybrid compiled/interpreted simulation of MOS circuits","authors":"L. McMurchie, Craig Anderson, G. Borriello","doi":"10.1109/EDAC.1991.206470","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206470","url":null,"abstract":"The authors have developed a switch-level simulator that combines the speed of compiled simulation algorithms with the flexibility and fast set-up times of interpretive schemes. Compiled simulation is fast for simple sub-circuits and slow for certain complex ones. Interpretive schemes have a fast set-up time, but are slow in simulating simple circuits because of the overhead of the interpreted data structures. The authors' hybrid scheme, based on COSMOS and MOSSIM II, offers the best of both approaches, reducing simulation time for a variety of common circuits and saving a factor of three or more in set-up time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"27 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121010912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A global router for sea-of-gates circuits
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206399
Kai-Win Lee, C. Sechen
{"title":"A global router for sea-of-gates circuits","authors":"Kai-Win Lee, C. Sechen","doi":"10.1109/EDAC.1991.206399","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206399","url":null,"abstract":"Describes a new global routing algorithm designed specifically for sea-of-gates circuits. The algorithm has been generalized to handle gate array and standard cell circuits. The main features of the algorithm are: (1) interconnection length minimization using a new Steiner tree generation method, (2) a two-stage coarse global routing method which seeks to even congestion, (3) a maze routing procedure which removes overflows and reduces the congestion, (4) vertical track assignment, and (5) congestion evening at the detailed global routing level. In tests on the MCNC benchmark circuits, the algorithm produced layouts with an average of 11% fewer routing tracks than the other algorithms. In tests on gate array benchmark circuits, the algorithm not only achieved uniform channel densities, but the maximum channel densities it produced are the lowest values that have ever been reported.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126190178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The automatic diagnosis of faults in analogue and mixed-signal circuits 模拟和混合信号电路故障的自动诊断
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206366
A. McKeon, A. Wakeling
{"title":"The automatic diagnosis of faults in analogue and mixed-signal circuits","authors":"A. McKeon, A. Wakeling","doi":"10.1109/EDAC.1991.206366","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206366","url":null,"abstract":"Describes a method detecting and locating faults automatically in analogue and mixed-signal circuits; the circuit representation used allows the tolerance of all component parameters to be considered simultaneously. Fault detection is accomplished by checking whether the measurements are consistent with a model of the circuit. Automatic fault diagnosis is accomplished by tracing the source of the inconsistency.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130904350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits 用于CMOS VLSI电路的阶跃等效电导时序模拟器
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206378
Shen Lin, M. Marek-Sadowska, E. Kuh
{"title":"SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits","authors":"Shen Lin, M. Marek-Sadowska, E. Kuh","doi":"10.1109/EDAC.1991.206378","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206378","url":null,"abstract":"Timing simulation has always been considered a crucial step in digital VLSI circuit design. Many researchers have addressed the issues of time efficiency vs. accuracy by using simpler device models and by simplifying the numerical algorithms. StepWise Equivalent Conductance (SWEC) simulation technique is an alternative which approximates the nonlinear transfer characteristic of the transistor with stepwise constant conductances. The authors demonstrate that the time step can be controlled to provide the necessary accuracy in the implicit integration algorithm. A timing simulator has been built based on this principle. The simulator can handle very large CMOS designs. Comparisons have been made with XPsim and SPECS2 using several examples. The results indicate that SWEC exhibits far better efficiency and accuracy.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Fast heuristic algorithms for finite state machine minimization 有限状态机最小化的快速启发式算法
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206388
L. N. Kannan, D. Sarma
{"title":"Fast heuristic algorithms for finite state machine minimization","authors":"L. N. Kannan, D. Sarma","doi":"10.1109/EDAC.1991.206388","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206388","url":null,"abstract":"A technique for the minimization of completely and incompletely specified sequential machines is described. By employing fast heuristic algorithms, it is shown that it is possible to effectively reduce large (121 states) finite state machines in reasonable computing time when compared to other methods. It has been shown that it is possible to achieve area/literal reductions in the range of 30-100% over unreduced machines using this technique.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
HERESY: a hybrid approach to automatic schematic generation (for VLSI) 异端:自动原理图生成的混合方法(用于VLSI)
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206438
T. Chiueh
{"title":"HERESY: a hybrid approach to automatic schematic generation (for VLSI)","authors":"T. Chiueh","doi":"10.1109/EDAC.1991.206438","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206438","url":null,"abstract":"An automatic schematic generation system called HERESY is presented, which represents a well-engineered combination of algorithmic and rule-based approaches. Equipped with a set of carefully-chosen evaluation criteria, HERESY is able to generate high-quality, reasonably general classes of schematic diagrams in an efficient way. A novel levelization algorithm that can detect and resolve arbitrary cyclic structures of a circuit is described. An example schematic generated by HERESY, together with its computational efficiency is also presented.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Technology mapping for a two-output RAM-based field programmable gate array 基于双输出ram的现场可编程门阵列的技术映射
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206465
D. Filo, J. C. Yang, F. Mailhot, G. Micheli
{"title":"Technology mapping for a two-output RAM-based field programmable gate array","authors":"D. Filo, J. C. Yang, F. Mailhot, G. Micheli","doi":"10.1109/EDAC.1991.206465","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206465","url":null,"abstract":"The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132409843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Floorplanning strategy for mixed analog-digital VLSI integrated circuits 混合模拟数字VLSI集成电路的平面规划策略
Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI: 10.1109/EDAC.1991.206422
L. París, G. Berbel, T. Osés
{"title":"Floorplanning strategy for mixed analog-digital VLSI integrated circuits","authors":"L. París, G. Berbel, T. Osés","doi":"10.1109/EDAC.1991.206422","DOIUrl":"https://doi.org/10.1109/EDAC.1991.206422","url":null,"abstract":"A generalization of techniques already in use in digital floorplanning, introducing three types of blocks: analog, digital and mixed, allows the implementation of a floorplanner suitable for mixed analog digital ICs. It makes use of the properties of the blocks to employ different approaches depending on their composition. It makes extensive usage of slicing structures to calculate optimal dimensions and orientations of the blocks, while taking into consideration the constraints due to the coexistence of analog and digital circuitry in the same IC.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133411180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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