{"title":"Hybrid compiled/interpreted simulation of MOS circuits","authors":"L. McMurchie, Craig Anderson, G. Borriello","doi":"10.1109/EDAC.1991.206470","DOIUrl":null,"url":null,"abstract":"The authors have developed a switch-level simulator that combines the speed of compiled simulation algorithms with the flexibility and fast set-up times of interpretive schemes. Compiled simulation is fast for simple sub-circuits and slow for certain complex ones. Interpretive schemes have a fast set-up time, but are slow in simulating simple circuits because of the overhead of the interpreted data structures. The authors' hybrid scheme, based on COSMOS and MOSSIM II, offers the best of both approaches, reducing simulation time for a variety of common circuits and saving a factor of three or more in set-up time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"27 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The authors have developed a switch-level simulator that combines the speed of compiled simulation algorithms with the flexibility and fast set-up times of interpretive schemes. Compiled simulation is fast for simple sub-circuits and slow for certain complex ones. Interpretive schemes have a fast set-up time, but are slow in simulating simple circuits because of the overhead of the interpreted data structures. The authors' hybrid scheme, based on COSMOS and MOSSIM II, offers the best of both approaches, reducing simulation time for a variety of common circuits and saving a factor of three or more in set-up time.<>