基于双输出ram的现场可编程门阵列的技术映射

D. Filo, J. C. Yang, F. Mailhot, G. Micheli
{"title":"基于双输出ram的现场可编程门阵列的技术映射","authors":"D. Filo, J. C. Yang, F. Mailhot, G. Micheli","doi":"10.1109/EDAC.1991.206465","DOIUrl":null,"url":null,"abstract":"The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"58","resultStr":"{\"title\":\"Technology mapping for a two-output RAM-based field programmable gate array\",\"authors\":\"D. Filo, J. C. Yang, F. Mailhot, G. Micheli\",\"doi\":\"10.1109/EDAC.1991.206465\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"58\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206465\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206465","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 58

摘要

作者提出了一种将技术映射到现场可编程门阵列(fpga)的新方法。他们考虑了一类基于双输出五输入ram单元的fpga,用于实现组合逻辑功能。描述了一种启发式的技术映射算法,该算法在逻辑功能共享信息的驱动下,对FPGA原语中的电路进行分解。作者在Hydra程序中实现了该算法。实验结果表明,该算法在绘图领域比现有程序平均提高了20% ~ 25%,计算时间提高了67倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Technology mapping for a two-output RAM-based field programmable gate array
The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time.<>
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