A global router for sea-of-gates circuits

Abstract

Describes a new global routing algorithm designed specifically for sea-of-gates circuits. The algorithm has been generalized to handle gate array and standard cell circuits. The main features of the algorithm are: (1) interconnection length minimization using a new Steiner tree generation method, (2) a two-stage coarse global routing method which seeks to even congestion, (3) a maze routing procedure which removes overflows and reduces the congestion, (4) vertical track assignment, and (5) congestion evening at the detailed global routing level. In tests on the MCNC benchmark circuits, the algorithm produced layouts with an average of 11% fewer routing tracks than the other algorithms. In tests on gate array benchmark circuits, the algorithm not only achieved uniform channel densities, but the maximum channel densities it produced are the lowest values that have ever been reported.<>