TAS: an accurate timing analyser for CMOS VLSI

Abstract

A CMOS timing analyser using accurate delay models is presented. Switch-level analytic delays are derived from I/V characteristics of short-channel MOSFETS. A significant improvement in accuracy is obtained from the analysis of pertinent capacitances, modeling conflicts and slope effects in CMOS gates. The program handles large-scale circuits and gives the worst-case delays between circuit terminals in realistic CPU times. The algorithm for path analysis is described. It is concluded that the run time is linear with the number of transistors, the accuracy within 5% over a wide range of design types.<>