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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)最新文献

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A GSM/EDGE/WCDMA modulator with on-chip D/A converter for base station 一种GSM/EDGE/WCDMA调制器，带有片上D/A转换器，用于基站
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993023
J. Vankka, J. Ketola, Olli Väänänen, J. Sommarek, M. Kosunen, K. Halonen
{"title":"A GSM/EDGE/WCDMA modulator with on-chip D/A converter for base station","authors":"J. Vankka, J. Ketola, Olli Väänänen, J. Sommarek, M. Kosunen, K. Halonen","doi":"10.1109/ISSCC.2002.993023","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993023","url":null,"abstract":"A modulator with a 14 b on-chip D/A converter occupies 22.09 mm/sup 2/ in 0.35 μm CMOS technology and dissipates 1.7 W at 3.3 V with a 110 MHz clock. A digital programmable up/down unit enables power ramping on a time-slot basis. The modulator fulfils the spectrum, phase and EVM specifications of GSM, EDGE and WCDMA.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114801201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An offset cancellation bit-line sensing scheme for low-voltage DRAM applications 一种用于低压DRAM应用的偏移抵消位线传感方案
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992170
Sang-Hoon Hong, Si-Hong Kim, Se Jun Kim, J. Wee, Jin-Yong Chung
{"title":"An offset cancellation bit-line sensing scheme for low-voltage DRAM applications","authors":"Sang-Hoon Hong, Si-Hong Kim, Se Jun Kim, J. Wee, Jin-Yong Chung","doi":"10.1109/ISSCC.2002.992170","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992170","url":null,"abstract":"Offset-cancellation provides low-voltage DRAM operation. The offset cancelling bit-line sense amplifiers are pitch-matched to the conventional 0.16 /spl mu/m DRAM cell array without process modifications. Results indicate better refresh characteristics than conventional bit-line sense amplifiers even at 1.5 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-noise low-offset chopper-stabilized capacitive-readout amplifier for CMOS MEMS accelerometers 用于CMOS MEMS加速度计的低噪声低偏置斩波稳定电容读出放大器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993115
Jiangfeng Wu, G. Fedder, L. Carley
{"title":"A low-noise low-offset chopper-stabilized capacitive-readout amplifier for CMOS MEMS accelerometers","authors":"Jiangfeng Wu, G. Fedder, L. Carley","doi":"10.1109/ISSCC.2002.993115","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993115","url":null,"abstract":"A CMOS chopper-stabilized amplifier with both DC and AC offset cancellation, for capacitive readout of motion in MEMS structures, achieves 40 nV//spl radic/HZ noise floor, 10 mV DC offset, and 40 dB sensor offset reduction. The amplifier, integrated into a CMOS-MEMS accelerometer, achieves 50 /spl mu/g//spl radic/Hz noise floor.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"441 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125744142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
An integrated 802.11a baseband and MAC processor 集成802.11a基带和MAC处理器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992137
J. Thomson, Bevan Baas, Elizabeth M Cooper, J. Gilbert, George Hsieh, P. Husted, Aparna Lokanathan, Jeffrey S Kuskin, David Mccracken, Bill Mcfarland, Teresa H Meng, D. Nakahira, S. Ng, Mahesh Rattehalli, Jeff L Smith, Ravi Subramanian, Lars Thon, Yi-Hsiu Wang, Robert Yu, Xiaoru Zhang, P. Cole, K. Hanley, D. Jianto, L. Johnson, C. Khan, S. Lee, S. Montoya, S. Padnos, A. Rabii, S. Tehrani, J. Wong, Zheng
{"title":"An integrated 802.11a baseband and MAC processor","authors":"J. Thomson, Bevan Baas, Elizabeth M Cooper, J. Gilbert, George Hsieh, P. Husted, Aparna Lokanathan, Jeffrey S Kuskin, David Mccracken, Bill Mcfarland, Teresa H Meng, D. Nakahira, S. Ng, Mahesh Rattehalli, Jeff L Smith, Ravi Subramanian, Lars Thon, Yi-Hsiu Wang, Robert Yu, Xiaoru Zhang, P. Cole, K. Hanley, D. Jianto, L. Johnson, C. Khan, S. Lee, S. Montoya, S. Padnos, A. Rabii, S. Tehrani, J. Wong, Zheng","doi":"10.1109/ISSCC.2002.992137","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992137","url":null,"abstract":"An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134027324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 111
A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology 基于3.1Gb/s串行链路技术的62Gb/s背板互连ASIC
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992944
P. Landman, A. Yee, R. Gu, B. Parthasarathy, V. Gupta, S. Ramaswamy, L. Dyson, P. Bosshart, J. Reynolds, M. Frannhagen, P. Fremrot, S. Johansson, K. Lewis, W. Lee
{"title":"A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology","authors":"P. Landman, A. Yee, R. Gu, B. Parthasarathy, V. Gupta, S. Ramaswamy, L. Dyson, P. Bosshart, J. Reynolds, M. Frannhagen, P. Fremrot, S. Johansson, K. Lewis, W. Lee","doi":"10.1109/ISSCC.2002.992944","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992944","url":null,"abstract":"A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A low-phase-noise low-phase-error 1.8 GHz quadrature CMOS VCO 低相位噪声低相位误差1.8 GHz正交CMOS压控振荡器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993046
P. Andreani
{"title":"A low-phase-noise low-phase-error 1.8 GHz quadrature CMOS VCO","authors":"P. Andreani","doi":"10.1109/ISSCC.2002.993046","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993046","url":null,"abstract":"A 1.8 GHz quadrature VCO in standard 0.35 /spl mu/m CMOS with three metal layers shows -140 dBc/Hz or less phase noise across an 18% tuning range, while drawing 25 mA from a 2 V power supply. The quadrature phase error between the VCO outputs is at most 0.25/spl deg/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130784409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
The core clock system on the next generation Itanium/spl trade/ microprocessor 下一代安腾/spl交易/微处理器的核心时钟系统
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992978
F. Anderson, J. Wells, E. Berta
{"title":"The core clock system on the next generation Itanium/spl trade/ microprocessor","authors":"F. Anderson, J. Wells, E. Berta","doi":"10.1109/ISSCC.2002.992978","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992978","url":null,"abstract":"A PLL generates a high-frequency core clock for a 1GHz processor by multiplying up the system clock. The clock is distributed across the 19/spl times/14 mm/sup 2/ core via a shielded, balanced, H-tree to the final pulsed gated buffers with <62 ps measured skew. Test features include phase shrinking and regional skew manipulation.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132914795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications Ovonic统一存储器-一种高性能非易失性存储器技术，适用于独立存储器和嵌入式应用程序
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992192
M. Gill, T. Lowrey, J. Park
{"title":"Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications","authors":"M. Gill, T. Lowrey, J. Park","doi":"10.1109/ISSCC.2002.992192","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992192","url":null,"abstract":"The development status of Ovonic Unified Memory (OUM), a phase-change non-volatile semiconductor memory technology for VLSI stand-alone memory and embedded applications, is discussed. Using 0.18 μm 3 V CMOS, cells from 5F/sup 2/ to 8F/sup 2/ are built in a charge-pump-free 4 Mb development vehicle. Direct overwrite, 10 ns reset times, 50 ns set times, and 1.0×10/sup 12/ cycling are achieved. At en-year data retention is projected at 120°C.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116400453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 117
A direct-conversion single-chip radio-modem for Bluetooth 用于蓝牙的直接转换单芯片无线电调制解调器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992112
Glenn Chang, Lars C. Jansson, Kevin J. Wang, Jorge Grilo, R. Montemayor, Chris Hull, Mark Lane, A. X. Estrada, Mike Anderson, Ian Galton, S. V. Kishore
{"title":"A direct-conversion single-chip radio-modem for Bluetooth","authors":"Glenn Chang, Lars C. Jansson, Kevin J. Wang, Jorge Grilo, R. Montemayor, Chris Hull, Mark Lane, A. X. Estrada, Mike Anderson, Ian Galton, S. V. Kishore","doi":"10.1109/ISSCC.2002.992112","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992112","url":null,"abstract":"A fully-integrated radio-modem using a direct-conversion receiver architecture achieves -83 dBm sensitivity at 0.1% BER, +40 dBm IIP2, and -5 dB and -40 dB adjacent and alternate channel blocking C/I, respectively. The radio consumes 39 mA in receive and 37 mA in transmit mode with a 2.7 V supply. The 19.5 mm/sup 2/ chip uses a 0.35 /spl mu/m 27 GHz f/sub T/ SOI BiCMOS process.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124646672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Highly-integrated SiGe BiCMOS WCDMA transmitter IC 高集成度SiGe BiCMOS WCDMA发射IC
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992208
A. Bellaouar, M. Frechette, A. Fridi, S. Embabi
{"title":"Highly-integrated SiGe BiCMOS WCDMA transmitter IC","authors":"A. Bellaouar, M. Frechette, A. Fridi, S. Embabi","doi":"10.1109/ISSCC.2002.992208","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992208","url":null,"abstract":"A highly-integrated SiGe BiCMOS WCDMA transmitter IC consists of VHF, UHF chains, and synthesizers. At 6 dBm output power, it consumes 79 mA at 2.7 V, with a 5% r.m.s. EVM and -42 dBc ACLR at 5 MHz offset. In-band and receive-band output noise are -128 and -135 Bm/Hz, respectively. Fully integrated PLLs use on-chip VCO tanks and require no off-chip loop filters.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124655322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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