下一代安腾/spl交易/微处理器的核心时钟系统

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992978

F. Anderson, J. Wells, E. Berta

{"title":"下一代安腾/spl交易/微处理器的核心时钟系统","authors":"F. Anderson, J. Wells, E. Berta","doi":"10.1109/ISSCC.2002.992978","DOIUrl":null,"url":null,"abstract":"A PLL generates a high-frequency core clock for a 1GHz processor by multiplying up the system clock. The clock is distributed across the 19/spl times/14 mm/sup 2/ core via a shielded, balanced, H-tree to the final pulsed gated buffers with <62 ps measured skew. Test features include phase shrinking and regional skew manipulation.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"The core clock system on the next generation Itanium/spl trade/ microprocessor\",\"authors\":\"F. Anderson, J. Wells, E. Berta\",\"doi\":\"10.1109/ISSCC.2002.992978\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PLL generates a high-frequency core clock for a 1GHz processor by multiplying up the system clock. The clock is distributed across the 19/spl times/14 mm/sup 2/ core via a shielded, balanced, H-tree to the final pulsed gated buffers with <62 ps measured skew. Test features include phase shrinking and regional skew manipulation.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992978\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 20

摘要

锁相环通过将系统时钟相乘，为1GHz处理器生成高频核心时钟。时钟通过屏蔽、平衡的h树分布在19/spl次/14 mm/sup 2/核心上，直至测量偏差<62 ps的最终脉冲门控缓冲器。测试特征包括相位收缩和区域倾斜操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The core clock system on the next generation Itanium/spl trade/ microprocessor

A PLL generates a high-frequency core clock for a 1GHz processor by multiplying up the system clock. The clock is distributed across the 19/spl times/14 mm/sup 2/ core via a shielded, balanced, H-tree to the final pulsed gated buffers with <62 ps measured skew. Test features include phase shrinking and regional skew manipulation.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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