基于3.1Gb/s串行链路技术的62Gb/s背板互连ASIC

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992944

P. Landman, A. Yee, R. Gu, B. Parthasarathy, V. Gupta, S. Ramaswamy, L. Dyson, P. Bosshart, J. Reynolds, M. Frannhagen, P. Fremrot, S. Johansson, K. Lewis, W. Lee

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引用次数: 17

摘要

62 Gb/s全双工总吞吐量的背板互连ASIC采用3.1 Gb/s串行链路技术组织成20个双向通道来实现带宽。该芯片的总误码率<5/spl倍/10/sup / 17/，采用0.18 /spl mu/m CMOS技术制造，在768引脚倒装芯片BGA封装中耗散9 W。

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A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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