Sang-Hoon Hong, Si-Hong Kim, Se Jun Kim, J. Wee, Jin-Yong Chung
{"title":"一种用于低压DRAM应用的偏移抵消位线传感方案","authors":"Sang-Hoon Hong, Si-Hong Kim, Se Jun Kim, J. Wee, Jin-Yong Chung","doi":"10.1109/ISSCC.2002.992170","DOIUrl":null,"url":null,"abstract":"Offset-cancellation provides low-voltage DRAM operation. The offset cancelling bit-line sense amplifiers are pitch-matched to the conventional 0.16 /spl mu/m DRAM cell array without process modifications. Results indicate better refresh characteristics than conventional bit-line sense amplifiers even at 1.5 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An offset cancellation bit-line sensing scheme for low-voltage DRAM applications\",\"authors\":\"Sang-Hoon Hong, Si-Hong Kim, Se Jun Kim, J. Wee, Jin-Yong Chung\",\"doi\":\"10.1109/ISSCC.2002.992170\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Offset-cancellation provides low-voltage DRAM operation. The offset cancelling bit-line sense amplifiers are pitch-matched to the conventional 0.16 /spl mu/m DRAM cell array without process modifications. Results indicate better refresh characteristics than conventional bit-line sense amplifiers even at 1.5 V.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.992170\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992170","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An offset cancellation bit-line sensing scheme for low-voltage DRAM applications
Offset-cancellation provides low-voltage DRAM operation. The offset cancelling bit-line sense amplifiers are pitch-matched to the conventional 0.16 /spl mu/m DRAM cell array without process modifications. Results indicate better refresh characteristics than conventional bit-line sense amplifiers even at 1.5 V.