An integrated 802.11a baseband and MAC processor

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992137

J. Thomson, Bevan Baas, Elizabeth M Cooper, J. Gilbert, George Hsieh, P. Husted, Aparna Lokanathan, Jeffrey S Kuskin, David Mccracken, Bill Mcfarland, Teresa H Meng, D. Nakahira, S. Ng, Mahesh Rattehalli, Jeff L Smith, Ravi Subramanian, Lars Thon, Yi-Hsiu Wang, Robert Yu, Xiaoru Zhang, P. Cole, K. Hanley, D. Jianto, L. Johnson, C. Khan, S. Lee, S. Montoya, S. Padnos, A. Rabii, S. Tehrani, J. Wong, Zheng

引用次数: 111

Abstract

An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.

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集成802.11a基带和MAC处理器

在0.25 /spl mu/m CMOS中，用于IEEE 802.11a WLAN标准的0.25 /spl mu/m CMOS混合信号基带和MAC处理器占用6.8/spl倍/6.8 mm/sup 2/，在196引脚的BGA封装中包含4.0M晶体管。发射和接收功耗分别为326mw和452mw。支持高达108 Mb/s的额外数据速率。MAC使用专用的控制和数据路径逻辑实现，并包括允许主机软件配置和控制其操作的寄存器。这产生了一个紧凑，节能的整体设计，不需要片外RAM或程序存储，但非常灵活。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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