2007 IEEE International Workshop on Memory Technology, Design and Testing最新文献

The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory 包裹选择门(WSG) SONOS存储器ONO厚度的极性依赖性

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547617

Kuan-Ti Wang, T. Chao, Woei-Cherng Wu, Chao‐Sung Lai

引用次数: 1

Future challenges and opportunities of the memory industry 记忆体产业未来的挑战与机遇

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547602

Changhyun Kim

引用次数: 0

A novel poly-Si nanowire TFT for nonvolatile memory applications 用于非易失性存储器的新型多晶硅纳米线TFT

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547618

H. Hsu, Horng-Chih Lin, Jian-Fu Huang, Tiao-Yuan Huang

引用次数: 0

A Controllable low-power dual-port embedded SRAM for DSP processor 一种用于DSP处理器的可控低功耗双端口嵌入式SRAM

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547610

Hao-I Yang, Ming-Hung Chang, Tay-Jyi Lin, Shih-Hao Ou, Siang-Sen Deng, Chih-Wei Liu, W. Hwang

引用次数: 2

Logic-compatible embedded NVM for RFID application 用于RFID应用的逻辑兼容嵌入式NVM

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547621

C. Kuo, J. Wang, Y. Chih, J. Wang, T. Yew, D. Shyu, J. Huang, K. Liu

引用次数: 2

Variability, margins, and unpredictability: Dealing with uncertainty in SRAM design 可变性、边际和不可预测性:处理SRAM设计中的不确定性

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547605

R. Aitken

引用次数: 0

High-performance SRAM in nanoscale CMOS: Design challenges and techniques 纳米级CMOS中的高性能SRAM:设计挑战和技术

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547603

C. Chuang, S. Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, R. Rao

{"title":"High-performance SRAM in nanoscale CMOS: Design challenges and techniques","authors":"C. Chuang, S. Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, R. Rao","doi":"10.1109/MTDT.2007.4547603","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547603","url":null,"abstract":"This paper reviews the design challenges and techniques of high-performance SRAM in the \"End of Scaling\" nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage, degradation of noise margin due to VT scatter caused by process variations and random dopant fluctuation, and long term reliability degradation such as NBTI, are addressed. Design directions and leakage/variation/degradation tolerant SRAM circuit techniques to mitigate various performance and reliability constraints in conventional planar CMOS technology are discussed. Examples are given and merits discussed for cell isolation and strength preservation, thin cell layout, bit-line and word-line leakage mitigation, migration to large signal read-out, undamped bit-line, dual-supply, dynamic Read/Write supply, floating power-line, header/footer power-gating structures, Read- and Write-assist circuits, leakage/variation detection and compensation techniques, word-line and bit-line pulsing schemes, gate leakage tolerant design, and NBTI tolerant design. Alternative cell structures, such as asymmetrical SRAM, 7T, and 8T SRAMs, which decouple the cell storage node from the Read-disturb and half-select disturb to improve the SNM are discussed. Finally, some design issues and opportunities in emerging technologies such as FD/SOI and multi-gate FinFET are illustrated.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130320521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

An automatic design for flash memory testing 一种闪存测试的自动设计

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547615

Wei-Lun Wang, Zheng-Wei Song

引用次数: 4

How far can we go in wireless testing of memory chips and wafers? 在存储芯片和晶圆的无线测试方面，我们能走多远?

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547611

Cheng-Wen Wu

引用次数: 3

Embedded SRAM trend in nano-scale CMOS 纳米级CMOS的嵌入式SRAM趋势

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547608

H. Yamauchi

引用次数: 21