用于非易失性存储器的新型多晶硅纳米线TFT

2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI:10.1109/MTDT.2007.4547618

H. Hsu, Horng-Chih Lin, Jian-Fu Huang, Tiao-Yuan Huang

{"title":"用于非易失性存储器的新型多晶硅纳米线TFT","authors":"H. Hsu, Horng-Chih Lin, Jian-Fu Huang, Tiao-Yuan Huang","doi":"10.1109/MTDT.2007.4547618","DOIUrl":null,"url":null,"abstract":"A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A novel poly-Si nanowire TFT for nonvolatile memory applications\",\"authors\":\"H. Hsu, Horng-Chih Lin, Jian-Fu Huang, Tiao-Yuan Huang\",\"doi\":\"10.1109/MTDT.2007.4547618\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.\",\"PeriodicalId\":422226,\"journal\":{\"name\":\"2007 IEEE International Workshop on Memory Technology, Design and Testing\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-12-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Workshop on Memory Technology, Design and Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2007.4547618\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2007.4547618","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

制备了一种具有独立双栅结构的新型聚硅纳米线TFT-SONOS器件并对其进行了表征。研究了其电学特性，包括编程性能和擦除性能。增加适当的顶栅偏置可以提高编程效率，从而产生更大的内存窗口。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel poly-Si nanowire TFT for nonvolatile memory applications

A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2007 IEEE International Workshop on Memory Technology, Design and Testing

自引率

0.00%

发文量