Logic-compatible embedded NVM for RFID application

C. Kuo, J. Wang, Y. Chih, J. Wang, T. Yew, D. Shyu, J. Huang, K. Liu
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引用次数: 2

Abstract

In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation. The minimum VCC for read operation can be as low as 0.68 V at -40degC. Macro size of 1024-bits IP is only 0.215 mm2.
用于RFID应用的逻辑兼容嵌入式NVM
本文描述了一种用于射频识别(RFID)应用的逻辑进程兼容嵌入式非易失性存储器(NVM)宏的设计。介绍了采用0.18 μ m标准CMOS工艺制作的1024位NVM测试芯片原型。表征结果表明,写操作的写功率仅为90uw,读操作的写功率为2uw @0.5 MHz。在-40°c时,读取操作的最小VCC可低至0.68 V。1024位IP的宏尺寸仅为0.215 mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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