C. Kuo, J. Wang, Y. Chih, J. Wang, T. Yew, D. Shyu, J. Huang, K. Liu
{"title":"用于RFID应用的逻辑兼容嵌入式NVM","authors":"C. Kuo, J. Wang, Y. Chih, J. Wang, T. Yew, D. Shyu, J. Huang, K. Liu","doi":"10.1109/MTDT.2007.4547621","DOIUrl":null,"url":null,"abstract":"In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation. The minimum VCC for read operation can be as low as 0.68 V at -40degC. Macro size of 1024-bits IP is only 0.215 mm2.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Logic-compatible embedded NVM for RFID application\",\"authors\":\"C. Kuo, J. Wang, Y. Chih, J. Wang, T. Yew, D. Shyu, J. Huang, K. Liu\",\"doi\":\"10.1109/MTDT.2007.4547621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation. The minimum VCC for read operation can be as low as 0.68 V at -40degC. Macro size of 1024-bits IP is only 0.215 mm2.\",\"PeriodicalId\":422226,\"journal\":{\"name\":\"2007 IEEE International Workshop on Memory Technology, Design and Testing\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-12-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Workshop on Memory Technology, Design and Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2007.4547621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2007.4547621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Logic-compatible embedded NVM for RFID application
In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation. The minimum VCC for read operation can be as low as 0.68 V at -40degC. Macro size of 1024-bits IP is only 0.215 mm2.
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