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2007 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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System-in-Package design/testing in memory package 系统封装设计/内存封装测试
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547601
S. Chen
{"title":"System-in-Package design/testing in memory package","authors":"S. Chen","doi":"10.1109/MTDT.2007.4547601","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547601","url":null,"abstract":"Summary form only given. Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions. SIP is becoming the mainstream in assembly, which is able to short the design cycle time and speed up the new product introduction, especially in the mobile phone, hand held product and memory products. Stack dice, PoP (package-on-package) is mature and has been widely and growing up the market share. Embedded dice/substrate, fan-out-WLCSP, and TSV (through silicon via) are coming soon. Many new technology, especially for memory has been developed, they will be discussed during the sections.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115993867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-gating current test for static RAM in nanotechnologies 纳米技术中静态RAM的功率门控电流测试
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547614
Yuan-Wei Chao, Hsin-Ling Chen, Chih-Jong Chen, Tsung-Chu Huang
{"title":"Power-gating current test for static RAM in nanotechnologies","authors":"Yuan-Wei Chao, Hsin-Ling Chen, Chih-Jong Chen, Tsung-Chu Huang","doi":"10.1109/MTDT.2007.4547614","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547614","url":null,"abstract":"Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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