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2007 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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RAMSES-D: DRAM fault simulator supporting weighted coupling fault RAMSES-D:支持加权耦合故障的DRAM故障模拟器
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547612
Yu-Tsao Hsing, Song-Guang Wu, Cheng-Wen Wu
{"title":"RAMSES-D: DRAM fault simulator supporting weighted coupling fault","authors":"Yu-Tsao Hsing, Song-Guang Wu, Cheng-Wen Wu","doi":"10.1109/MTDT.2007.4547612","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547612","url":null,"abstract":"Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the concept of weighted coupling fault targeting DRAM. We propose a weighted fault coverage function with assigning weight parameters to coupling faults. With the weighted function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between different memory configurations.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"911 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123269029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Next-generation non-volatile memory 下一代非易失性存储器
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547616
M. Kao
{"title":"Next-generation non-volatile memory","authors":"M. Kao","doi":"10.1109/MTDT.2007.4547616","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547616","url":null,"abstract":"Recently, Next-generation non-volatile memories continue to receive great attention due to its scalability, rapid read and write performance, simple structure, and easy incorporation with CMOS process. There are many candidates for ideal non-volatile memory, such as Magnetro-resistive RAM (MRAM), Phase change RAM (PCRAM), and Resistive RAM (RRAM). This talk will discuss the strengths and weaknesses of different emerging non-volatile memory technologies and introduce the current status of the new non-volatile memory research program at ITRI.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121678667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improving the speed and power of compilable SRAM using dual-mode self-timed technique 利用双模自定时技术提高可编译SRAM的速度和性能
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547619
Meng-Fan Chang, Shu-Meng Yang, Kuang-Ting Chen, H. Liao, R. Lee
{"title":"Improving the speed and power of compilable SRAM using dual-mode self-timed technique","authors":"Meng-Fan Chang, Shu-Meng Yang, Kuang-Ting Chen, H. Liao, R. Lee","doi":"10.1109/MTDT.2007.4547619","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547619","url":null,"abstract":"A long bitline precharge time in the write operation and a wide wordline pulse width in the read operation dominate the cycle time of large-capacity compilable SRAMs. A data-dependent bitline leakage current causes timing skew and erodes the sensing margin of conventional replica-column controlled embedded SRAM. A dual-mode self-timed (DMST) technique is proposed to generate two individual timing for the read and write operations, unlike in conventional SRAMs, in which they have the same control timing, to reduce the cycle time and power consumption of the SRAM. The RC delay on bitlines, variations in the write response time of a bitcell and data-dependent bitline leakage current are considered in the DMST. The DMST technique reduces the cycle time and the write active power consumption by 16%~30.7% and 15%~22.7%, respectively for a 65 nm 512 Kb SRAM.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133584114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Value creation and technological convergence by evolution of embedded non-volatile memory 嵌入式非易失性存储器的进化带来的价值创造和技术融合
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547604
H. Hidaka
{"title":"Value creation and technological convergence by evolution of embedded non-volatile memory","authors":"H. Hidaka","doi":"10.1109/MTDT.2007.4547604","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547604","url":null,"abstract":"Flash-MCU, micro-controller with embedded flash memory storage (eFlash), has seen a tremendous up-surge in real-time control application markets, with assumed 20% CAGR. The programmable code storage provided by eFlash contributes to production cost reduction and real-time adaptive control applications, realizing a value innovation with remarkable cost/value advantage. The diversified advanced eFlash technology for converging flash-MCU products challenges new market drivers like automotive and smart-IC cards. Current status and future directions of flash-MCU in view of how on-chip programmability function evolution contributes to innovate MCU/SOC applications are overviewed. The 3rd generation MCU products as realized by NV-RAM concepts will drive a convergence into unified technology by value creation opportunities provided.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133887542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Resilient SRAM design using BIST-assisted Timing Tracking 采用bist辅助定时跟踪的弹性SRAM设计
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547613
Ya-Chun Lai, Shi-Yu Huang
{"title":"Resilient SRAM design using BIST-assisted Timing Tracking","authors":"Ya-Chun Lai, Shi-Yu Huang","doi":"10.1109/MTDT.2007.4547613","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547613","url":null,"abstract":"In this paper, an SRAM design using BIST-assisted timing-tracking (BITT) scheme to improve parametric yield by 76.7% as compared with the traditional timing-tracking method has been presented. This scheme combines reconfigurable delay line, which is tunable by memory BIST, with dummy bitline timing tracking. Consequently, the timing skew due to cell current fluctuations and imbalanced sense amplifiers can both be taken into account so as to provide more flexible timing control for future nanometer technologies.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Future trend of flash memories
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547607
Yi-Chou Chen, R. Liu
{"title":"Future trend of flash memories","authors":"Yi-Chou Chen, R. Liu","doi":"10.1109/MTDT.2007.4547607","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547607","url":null,"abstract":"Summary form only given. Flash memories have provided reliable solid-state storage solutions for over twenty years. In the last few years we have seen an explosive growth of NAND flash, fueled by digital camera, USB, MP3, iPhone and numerous new mobile applications. However, this phenomenal boom is silently threatened by scaling limitations intrinsically built into the flash devices. Old challenges such as scaling the charge tunneling oxide have remained unconquered (and now proven unconquerable) for nearly a decade, and new challenges such as floating gate cross talk become more serious with scaling. Will flash technology be simply a brief flash in the history of semiconductor? In this talk we will start with the flash memory technology and market trend. We will then discuss the scaling issues for NOR and NAND floating gate devices, and their fundamental limitations. Potential solutions, including both new devices and architecture and completely new types of non-volatile memory will then be discussed. Recent progresses in new NAND and NOR flash memory solutions or substitutes such as TANOS, BE-SONOS, 3D stacking and phase change memory will be examined in considerable details.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Process variability considerations in the design of an eSRAM eSRAM设计中工艺可变性的考虑
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547609
M. Yap, San Min, P. Maurine, M. Robert, Lirmm, France M Montpellier, Bastian
{"title":"Process variability considerations in the design of an eSRAM","authors":"M. Yap, San Min, P. Maurine, M. Robert, Lirmm, France M Montpellier, Bastian","doi":"10.1109/MTDT.2007.4547609","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547609","url":null,"abstract":"Process variation constitutes a serious hindrance to the performance of SRAMs, since memories require bigger design margins for their proper operations. In this paper, we propose a new dummy bit line driver structure and its statistical sizing method to reduce the sensitivity of the memory with respect to process variations, while improving the read timing margin. The dummy bit line driver is an essential component in a self-timed memory during a read operation. It triggers the sense amplifier at the appropriate time when bit line is discharged. We considered a 256 kb SRAM in a 90 nm technology node.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Vulnerability analysis of secure USB flash drives 安全USB闪存驱动器的漏洞分析
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547620
Hanjae Jeong, Younsung Choi, Woongryel Jeon, Fei Yang, Yunho Lee, Seungjoo Kim, Dongho Won
{"title":"Vulnerability analysis of secure USB flash drives","authors":"Hanjae Jeong, Younsung Choi, Woongryel Jeon, Fei Yang, Yunho Lee, Seungjoo Kim, Dongho Won","doi":"10.1109/MTDT.2007.4547620","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547620","url":null,"abstract":"USB flash drive without any security function causes the exposure of private information. So new USB flash drive supported security function was invented to compensate for the problem. In this paper, we analyze vulnerability of 6 famous secure USB flash drives, and demonstrate that password can be exposed on communication between the secure USB flash drive and PC. Also we show the vulnerability on the data recovery and the S/W bug of secure USB flash drive.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130350152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
An ALU cluster intellectual property for magnetic RAM media applications platform 一种基于ALU集群知识产权的磁性RAM媒体应用平台
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547622
C. Liou, H. Chiueh
{"title":"An ALU cluster intellectual property for magnetic RAM media applications platform","authors":"C. Liou, H. Chiueh","doi":"10.1109/MTDT.2007.4547622","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547622","url":null,"abstract":"The next generation memory, magnetic random access memory (MRAM), is a high-profile choice of embedded memory in modern applications. Features of the novel memory make it suitable for universal memory applications. Besides, as the evolution of information technology, embedded systems with media applications for portable devices are more important in modern life. In both of the perspectives mentioned above, a processing element called arithmetic logic unit (ALU) cluster intellectual property (IP) is designed and implemented to be integrated with MRAM and the platform baseboard in this work. To stack these components such as an ALU cluster, MRAM and versatile baseboard provides a development, verification and demonstration platform for the highly-expected MRAM. The proposed ALU cluster IP with advanced microcontroller bus architecture (AMBA) interface is taped out using TSMC 0.15 um technology and operates at 100 MHz. The chip area is 3.9*3.9 mm2 and gate count is 0.2 million. A 4-layer FRP printed circuit board (PCB) is designed and fabricated as the daughter card for system integration. The daughter card carries the designed chip is integrated to ARM versatile platform board and the PCB of MRAM as the system integration and application development environment.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116079836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling trend of the Flash memory for file storage 用于文件存储的Flash缩放趋势
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547606
R. Shirota
{"title":"Scaling trend of the Flash memory for file storage","authors":"R. Shirota","doi":"10.1109/MTDT.2007.4547606","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547606","url":null,"abstract":"This paper describes the review of flash memory. First, the fundamental device and design characteristics of flash memory are shown. Next, recent developments of flash memory are reviewed. The flash memory cell structure can be classified into two types; floating gate type and charge trap type. Both current technologies are introduced. Third, road map and scaling issues of flash memory are summarized.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124807177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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