2007 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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Value creation and technological convergence by evolution of embedded non-volatile memory 嵌入式非易失性存储器的进化带来的价值创造和技术融合
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547604
H. Hidaka
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引用次数: 1
An ALU cluster intellectual property for magnetic RAM media applications platform 一种基于ALU集群知识产权的磁性RAM媒体应用平台
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547622
C. Liou, H. Chiueh
{"title":"An ALU cluster intellectual property for magnetic RAM media applications platform","authors":"C. Liou, H. Chiueh","doi":"10.1109/MTDT.2007.4547622","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547622","url":null,"abstract":"The next generation memory, magnetic random access memory (MRAM), is a high-profile choice of embedded memory in modern applications. Features of the novel memory make it suitable for universal memory applications. Besides, as the evolution of information technology, embedded systems with media applications for portable devices are more important in modern life. In both of the perspectives mentioned above, a processing element called arithmetic logic unit (ALU) cluster intellectual property (IP) is designed and implemented to be integrated with MRAM and the platform baseboard in this work. To stack these components such as an ALU cluster, MRAM and versatile baseboard provides a development, verification and demonstration platform for the highly-expected MRAM. The proposed ALU cluster IP with advanced microcontroller bus architecture (AMBA) interface is taped out using TSMC 0.15 um technology and operates at 100 MHz. The chip area is 3.9*3.9 mm2 and gate count is 0.2 million. A 4-layer FRP printed circuit board (PCB) is designed and fabricated as the daughter card for system integration. The daughter card carries the designed chip is integrated to ARM versatile platform board and the PCB of MRAM as the system integration and application development environment.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116079836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling trend of the Flash memory for file storage 用于文件存储的Flash缩放趋势
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547606
R. Shirota
{"title":"Scaling trend of the Flash memory for file storage","authors":"R. Shirota","doi":"10.1109/MTDT.2007.4547606","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547606","url":null,"abstract":"This paper describes the review of flash memory. First, the fundamental device and design characteristics of flash memory are shown. Next, recent developments of flash memory are reviewed. The flash memory cell structure can be classified into two types; floating gate type and charge trap type. Both current technologies are introduced. Third, road map and scaling issues of flash memory are summarized.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124807177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
System-in-Package design/testing in memory package 系统封装设计/内存封装测试
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547601
S. Chen
{"title":"System-in-Package design/testing in memory package","authors":"S. Chen","doi":"10.1109/MTDT.2007.4547601","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547601","url":null,"abstract":"Summary form only given. Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions. SIP is becoming the mainstream in assembly, which is able to short the design cycle time and speed up the new product introduction, especially in the mobile phone, hand held product and memory products. Stack dice, PoP (package-on-package) is mature and has been widely and growing up the market share. Embedded dice/substrate, fan-out-WLCSP, and TSV (through silicon via) are coming soon. Many new technology, especially for memory has been developed, they will be discussed during the sections.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115993867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-gating current test for static RAM in nanotechnologies 纳米技术中静态RAM的功率门控电流测试
2007 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2007-12-03 DOI: 10.1109/MTDT.2007.4547614
Yuan-Wei Chao, Hsin-Ling Chen, Chih-Jong Chen, Tsung-Chu Huang
{"title":"Power-gating current test for static RAM in nanotechnologies","authors":"Yuan-Wei Chao, Hsin-Ling Chen, Chih-Jong Chen, Tsung-Chu Huang","doi":"10.1109/MTDT.2007.4547614","DOIUrl":"https://doi.org/10.1109/MTDT.2007.4547614","url":null,"abstract":"Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.","PeriodicalId":422226,"journal":{"name":"2007 IEEE International Workshop on Memory Technology, Design and Testing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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