Power-gating current test for static RAM in nanotechnologies

Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.