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GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995最新文献

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Use of gallium arsenide in medical applications 砷化镓在医学上的应用
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528951
K. Carr
{"title":"Use of gallium arsenide in medical applications","authors":"K. Carr","doi":"10.1109/GAAS.1995.528951","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528951","url":null,"abstract":"Microwave technology can be used to solve many medical problems where conventional technology has proven inadequate. This is particularly true for applications involving the generation of heat and the measurement and monitoring of temperature. Through cost-effective fabrication techniques based upon MMIC technology, this microwave technology has now become affordable. Several applications illustrating the significance of MMIC technology will be discussed. MMS's IV Injection-Site Monitor, for example, is based on passive microwave radiometric monitoring of subcutaneous tissue temperature. This technique is based upon the assumption that an unwanted accumulation of liquid (i.e., an extravasation into the tissue surrounding the infusion site) will result in a temperature differential. An extravasation is defined as the unwanted occurrence of infiltration of fluid during IV infusion beyond the vein or artery into the surrounding tissue. Extravasations of IV fluids in children can have serious consequences when gross extravasations occur. Skin necrosis can occur, which may require treatment with skin grafting. These advanced sequelae are less frequent in the adult population, but in newborns and young children they are much more prevalent and can be catastrophic. Neonates and infants are unable to communicate pain and are more prone to tissue necrosis. To address this application, the sensitive radiometer must be small and lightweight to meet the requirements of the pediatric (including neonatal) patient population.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134202653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ion-implanted WN 0.25 /spl mu/m gate MESFET fabricated using i-line photolithography for application to MMIC and digital IC 采用i线光刻技术制备的离子注入wn0.25 /spl μ m栅极MESFET，应用于MMIC和数字集成电路
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528969
E. Oh, Jeon-Wook Yang, Chul-Soon Park, K. Pyun
{"title":"Ion-implanted WN 0.25 /spl mu/m gate MESFET fabricated using i-line photolithography for application to MMIC and digital IC","authors":"E. Oh, Jeon-Wook Yang, Chul-Soon Park, K. Pyun","doi":"10.1109/GAAS.1995.528969","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528969","url":null,"abstract":"Straightforward WN 0.25 /spl mu/m gate MESFET process based on direct ion-implantation and i-line photolithography with double exposure process has produced high performance MESFETs. The maximum transconductance of 600 mS/mm and the k-factor of 450 ms/Vmm were obtained. As high as 65 GHz of cut-off frequency has been realized without any deembedding of parasitic effects. The MESFET shows the minimum noise figure of 0.87 dB and the associated gain of 9.97 dB at 12 GHz.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123600276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaAs 10 K gates gate array with digital variable delay macro cell 带有数字可变延迟宏单元的GaAs 10k门阵列
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.529021
A. Ohta, N. Higashisaka, M. Shimada, T. Heima, K. Hosogi, R. Ohmura, N. Tanino
{"title":"GaAs 10 K gates gate array with digital variable delay macro cell","authors":"A. Ohta, N. Higashisaka, M. Shimada, T. Heima, K. Hosogi, R. Ohmura, N. Tanino","doi":"10.1109/GAAS.1995.529021","DOIUrl":"https://doi.org/10.1109/GAAS.1995.529021","url":null,"abstract":"A GaAs 10 K gates gate array with digital variable delay macro cell is successfully developed for various measurement instrument applications. The digital delay circuit has 38.8 ns span and 50 ps resolution, and power dissipation is 300 mW, which is about half the dissipation for conventional analog delay circuits. It is possible for the gate array to include up to 8 delay macro cells with 800 gates. The gate array is fabricated using 0.5 /spl mu/m BPLDD (Buried p-layer Lightly Doped Drain) SAGFET (self-align gate metal FET) technology with triple metal layers. This chip is packed in a 132 pin ceramic QFP (quad flat package).","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115755883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
110 GHz amplifiers based on compact coplanar W-band receiver technology 基于紧凑共面w波段接收技术的110 GHz放大器
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528997
N. Schlechtweg, W. Haydl, J. Braunstein, P. Tasker, A. Bangert, W. Reinert, L. Verweyen, H. Massler, J. Seibel, K. Zufle, W. Bronner, T. Fink, A. Hulsmann, P. Hofmann, G. Kaufel, K. Kohler, B. Raynor, J. Schneider
{"title":"110 GHz amplifiers based on compact coplanar W-band receiver technology","authors":"N. Schlechtweg, W. Haydl, J. Braunstein, P. Tasker, A. Bangert, W. Reinert, L. Verweyen, H. Massler, J. Seibel, K. Zufle, W. Bronner, T. Fink, A. Hulsmann, P. Hofmann, G. Kaufel, K. Kohler, B. Raynor, J. Schneider","doi":"10.1109/GAAS.1995.528997","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528997","url":null,"abstract":"The potential of coplanar waveguide technology to build compact system modules is demonstrated by means of passive and active MMIC components. The realized passive structures comprise a Wilkinson combiner/divider and a capacitively loaded ultra miniature branch line coupler. Very good agreement between the measured and modelled data is achieved up to 120 GHz. A cascode MODFET small signal model working up to above 100 GHz has been developed for predictable MMIC design. Based on an accurate design database, a compact integrated amplifier utilizing cascode circuitry for application in the 100-120 GHz frequency band has been fabricated showing a measured maximum gain of 20 dB at 110 GHz. The gain is comparable to the result of a 2-stage amplifier fabricated using 0.1 /spl mu/m gate PHEMTs, while the chip size is reduced by more than 50%.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115540603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 2.5 Gb/s 16/spl times/16 bit crosspoint switch with fast programming 2.5 Gb/s 16/spl倍/16位交叉点开关，具有快速编程功能
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528958
R. Savarã, A. Turudic
{"title":"A 2.5 Gb/s 16/spl times/16 bit crosspoint switch with fast programming","authors":"R. Savarã, A. Turudic","doi":"10.1109/GAAS.1995.528958","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528958","url":null,"abstract":"A novel 2.5 Gb/s 16/spl times/16 bit crosspoint switch has been designed utilizing source coupled logic GaAs MESFET logic cells. The chip offers two methods of programming and is capable of a data path rate of 2.5 Gb/s, resulting in an aggregate bandwidth of 40 Gb/s.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
GaAs multibit delta-sigma A/D converters based upon a new comparator design 基于新型比较器的GaAs多位δ - σ A/D转换器设计
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.529017
R. Hickling, M. Yagi, H. H. Salman
{"title":"GaAs multibit delta-sigma A/D converters based upon a new comparator design","authors":"R. Hickling, M. Yagi, H. H. Salman","doi":"10.1109/GAAS.1995.529017","DOIUrl":"https://doi.org/10.1109/GAAS.1995.529017","url":null,"abstract":"In this paper, the design of multibit delta-sigma converters based upon a new comparator bank structure is described. The comparator bank approach eliminates the need for comparator threshold terminals, allowing each of the individual latched comparators to operate upon the same differential input signal. This new comparator design was incorporated into a complete four-bit delta-sigma modulator which was fabricated on a 0.6 /spl mu/m GaAs MESFET process.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Complementary GaAs(CGaAs): a high performance BiCMOS alternative 互补GaAs(CGaAs):一种高性能的BiCMOS替代品
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528953
B. Bernhardt, M. LaMacchia, J. Abrokwah, J. Hallmark, R. Lucero, B. Mathes, B. Crawforth, D. Foster, K. Clauss, S. Emmert, T. Lien, E. Lopez, V. Mazzotta, B. Oh
{"title":"Complementary GaAs(CGaAs): a high performance BiCMOS alternative","authors":"B. Bernhardt, M. LaMacchia, J. Abrokwah, J. Hallmark, R. Lucero, B. Mathes, B. Crawforth, D. Foster, K. Clauss, S. Emmert, T. Lien, E. Lopez, V. Mazzotta, B. Oh","doi":"10.1109/GAAS.1995.528953","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528953","url":null,"abstract":"A self aligned complementary GaAs (CGaAs) technology has been developed for low-power, high-speed digital and mixed-mode applications. Previous work has described the low voltage (0.9 to 1.5 V) and low power applications for portable products. Complementary digital circuits have demonstrated speed power performance of 0.01 /spl mu/W/MHz/gate at 0.9 V. This paper will describe our extensions to this process to provide even higher performance, at the expense of slightly higher static power dissipation. The extensions allow the flexibility to tune different sections of the circuitry to provide high performance where necessary with 5 GHz speeds using SCFL designs while still maintaining the ability to partition the system into areas with low standby power using CMOS-like designs. This modified process flow has demonstrated a mixed SCFL/complementary signal processor with a speed-power measurement of 0.16 /spl mu/W/MHz/gate while operating at >1 GHz, full complementary digital circuits at 500 MHz, RF MMIC and power circuits (400 MHz), utilizing the same process flow.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122659148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An MMIC chip set for a V-band phase-locked local oscillator 用于v波段锁相本地振荡器的MMIC芯片组
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.529007
A. Kanda, T. Hirota, H. Okazaki, M. Nakamae
{"title":"An MMIC chip set for a V-band phase-locked local oscillator","authors":"A. Kanda, T. Hirota, H. Okazaki, M. Nakamae","doi":"10.1109/GAAS.1995.529007","DOIUrl":"https://doi.org/10.1109/GAAS.1995.529007","url":null,"abstract":"A V-band full-monolithic voltage-controlled local oscillator (LO) chip set has been developed to realize a millimeter-wave synthesizer. The LO is composed of only two MMIC chips: one is a highly integrated multi-function MMIC for 15 GHz voltage-controlled oscillation and 15-30 GHz frequency doubling, and the other is for 30-60 GHz frequency doubling. Output power of 3.5 dBm/spl plusmn/1.5 dB and tuning performance of 55.6 to 60.3 GHz with SSB phase noise of less than -80 dBc/Hz @1 MHz offset are obtained. Each circuit is greatly reduced in size by using a uniplanar structure resulting in a total chip area of only 5.5 mm/sup 2/. To our knowledge, this is the most compact MMIC chip set for a V-band phase-locked oscillator.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122889893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A very-wide bandwidth digital VCO implemented in GaAs HBTs using frequency multiplication and division 在GaAs hbt中使用乘法和除法实现的一种极宽带宽数字压控振荡器
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.529018
P. Campbell, H. Greub, A. Garg, S. Steidl, C. Maier, S. Carlough, J. McDonald
{"title":"A very-wide bandwidth digital VCO implemented in GaAs HBTs using frequency multiplication and division","authors":"P. Campbell, H. Greub, A. Garg, S. Steidl, C. Maier, S. Carlough, J. McDonald","doi":"10.1109/GAAS.1995.529018","DOIUrl":"https://doi.org/10.1109/GAAS.1995.529018","url":null,"abstract":"A digital high-speed voltage-controlled oscillator (VCO) has been developed which uses frequency-multiplication and division to attain a wide frequency range of 0.5-13.66 GHz. The circuit is implemented in differential current-mode logic using GaAs-AlGaAs heterojunction bipolar transistors (HBTs). This paper discusses top-level system design as well as the design of several key components.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122699710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
GaAs multiplexer chip for ATM switching 用于ATM交换的GaAs多路复用芯片
GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995 Pub Date : 1995-10-29 DOI: 10.1109/GAAS.1995.528955
J. Jakobsen
{"title":"GaAs multiplexer chip for ATM switching","authors":"J. Jakobsen","doi":"10.1109/GAAS.1995.528955","DOIUrl":"https://doi.org/10.1109/GAAS.1995.528955","url":null,"abstract":"This paper describes the design of a GaAs multiplexer chip which can be used for the implementation of an ATM switch fabric. In order to achieve low power, a self-timed FIFO with automatic power off was designed. For high speed and low power a static flip-flop with push-pull output stage was also designed. The chip works at 1.15 GHz, corresponding to a throughput of 10 Gb/s. This is achieved at a power consumption of 1.2 W.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128912384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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