GaAs 10 K gates gate array with digital variable delay macro cell

Abstract

A GaAs 10 K gates gate array with digital variable delay macro cell is successfully developed for various measurement instrument applications. The digital delay circuit has 38.8 ns span and 50 ps resolution, and power dissipation is 300 mW, which is about half the dissipation for conventional analog delay circuits. It is possible for the gate array to include up to 8 delay macro cells with 800 gates. The gate array is fabricated using 0.5 /spl mu/m BPLDD (Buried p-layer Lightly Doped Drain) SAGFET (self-align gate metal FET) technology with triple metal layers. This chip is packed in a 132 pin ceramic QFP (quad flat package).