B. Bernhardt, M. LaMacchia, J. Abrokwah, J. Hallmark, R. Lucero, B. Mathes, B. Crawforth, D. Foster, K. Clauss, S. Emmert, T. Lien, E. Lopez, V. Mazzotta, B. Oh
{"title":"互补GaAs(CGaAs):一种高性能的BiCMOS替代品","authors":"B. Bernhardt, M. LaMacchia, J. Abrokwah, J. Hallmark, R. Lucero, B. Mathes, B. Crawforth, D. Foster, K. Clauss, S. Emmert, T. Lien, E. Lopez, V. Mazzotta, B. Oh","doi":"10.1109/GAAS.1995.528953","DOIUrl":null,"url":null,"abstract":"A self aligned complementary GaAs (CGaAs) technology has been developed for low-power, high-speed digital and mixed-mode applications. Previous work has described the low voltage (0.9 to 1.5 V) and low power applications for portable products. Complementary digital circuits have demonstrated speed power performance of 0.01 /spl mu/W/MHz/gate at 0.9 V. This paper will describe our extensions to this process to provide even higher performance, at the expense of slightly higher static power dissipation. The extensions allow the flexibility to tune different sections of the circuitry to provide high performance where necessary with 5 GHz speeds using SCFL designs while still maintaining the ability to partition the system into areas with low standby power using CMOS-like designs. This modified process flow has demonstrated a mixed SCFL/complementary signal processor with a speed-power measurement of 0.16 /spl mu/W/MHz/gate while operating at >1 GHz, full complementary digital circuits at 500 MHz, RF MMIC and power circuits (400 MHz), utilizing the same process flow.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Complementary GaAs(CGaAs): a high performance BiCMOS alternative\",\"authors\":\"B. Bernhardt, M. LaMacchia, J. Abrokwah, J. Hallmark, R. Lucero, B. Mathes, B. Crawforth, D. Foster, K. Clauss, S. Emmert, T. Lien, E. Lopez, V. Mazzotta, B. Oh\",\"doi\":\"10.1109/GAAS.1995.528953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A self aligned complementary GaAs (CGaAs) technology has been developed for low-power, high-speed digital and mixed-mode applications. Previous work has described the low voltage (0.9 to 1.5 V) and low power applications for portable products. Complementary digital circuits have demonstrated speed power performance of 0.01 /spl mu/W/MHz/gate at 0.9 V. This paper will describe our extensions to this process to provide even higher performance, at the expense of slightly higher static power dissipation. The extensions allow the flexibility to tune different sections of the circuitry to provide high performance where necessary with 5 GHz speeds using SCFL designs while still maintaining the ability to partition the system into areas with low standby power using CMOS-like designs. This modified process flow has demonstrated a mixed SCFL/complementary signal processor with a speed-power measurement of 0.16 /spl mu/W/MHz/gate while operating at >1 GHz, full complementary digital circuits at 500 MHz, RF MMIC and power circuits (400 MHz), utilizing the same process flow.\",\"PeriodicalId\":422183,\"journal\":{\"name\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1995.528953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1995.528953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Complementary GaAs(CGaAs): a high performance BiCMOS alternative
A self aligned complementary GaAs (CGaAs) technology has been developed for low-power, high-speed digital and mixed-mode applications. Previous work has described the low voltage (0.9 to 1.5 V) and low power applications for portable products. Complementary digital circuits have demonstrated speed power performance of 0.01 /spl mu/W/MHz/gate at 0.9 V. This paper will describe our extensions to this process to provide even higher performance, at the expense of slightly higher static power dissipation. The extensions allow the flexibility to tune different sections of the circuitry to provide high performance where necessary with 5 GHz speeds using SCFL designs while still maintaining the ability to partition the system into areas with low standby power using CMOS-like designs. This modified process flow has demonstrated a mixed SCFL/complementary signal processor with a speed-power measurement of 0.16 /spl mu/W/MHz/gate while operating at >1 GHz, full complementary digital circuits at 500 MHz, RF MMIC and power circuits (400 MHz), utilizing the same process flow.