H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang
{"title":"Millimeter-Wave Band CMOS RF Phased-Array Transceiver IC Designs for 5G Applications","authors":"H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang","doi":"10.1109/IEDM13553.2020.9371948","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371948","url":null,"abstract":"This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, POUT, stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows POUT/Ch. of >6.0dBm at EVM of -34dB (800MHz) and PDC/Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and PDC/Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of <-113dBm/100MHz in the 5G NR base-station system.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"35 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131563294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Garcia Bardon, P. Wuytens, L. Ragnarsson, G. Mirabelli, D. Jang, G. Willems, A. Mallik, A. Spessot, J. Ryckaert, B. Parvais
{"title":"DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies","authors":"M. Garcia Bardon, P. Wuytens, L. Ragnarsson, G. Mirabelli, D. Jang, G. Willems, A. Mallik, A. Spessot, J. Ryckaert, B. Parvais","doi":"10.1109/IEDM13553.2020.9372004","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372004","url":null,"abstract":"Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business and of regulations. The progress of Design Technology Co- Optimization (DTCO) methodologies and tools, building transversal knowledge from manufacturing to design, provides an opportunity to develop a framework for early sustainability assessments of logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To demonstrate this approach, we evaluate the energy and water consumption as well as the greenhouse gas emissions trends from processing logic nodes from iN28 to iN3 with different scaling scenarios.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128347876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mochizuki, M. Bhuiyan, H. Zhou, J. Zhang, E. Stuckert, J. Li, K. Zhao, M. Wang, V. Basker, N. Loubet, D. Guo, B. Haran, H. Bu
{"title":"Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel","authors":"S. Mochizuki, M. Bhuiyan, H. Zhou, J. Zhang, E. Stuckert, J. Li, K. Zhao, M. Wang, V. Basker, N. Loubet, D. Guo, B. Haran, H. Bu","doi":"10.1109/IEDM13553.2020.9372041","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372041","url":null,"abstract":"Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si<inf>1-x</inf>Ge<inf>x</inf> channel have been fabricated to explore their electrical benefits. The Si<inf>1-x</inf>Ge<inf>x</inf> NS channel structure with high crystalline quality and 1GPa compressive stress has been realized for the first time. Systematic study has been performed to understand the effect of epitaxial Si<inf>1-x</inf>Ge<inf>x</inf> thickness, Ge fraction, and Si cap thickness on the Si<inf>1-x</inf>Ge<inf>x</inf> NS channel device characteristics. It is found that the compressively strained Si<inf>1-x</inf>Ge<inf>x</inf> NS channel provides a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40% while maintaining an excellent subthreshold slope of below 70 mV/dec.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1993 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaochen Peng, W. Chakraborty, Ankit Kaul, Wonbo Shim, M. Bakir, S. Datta, Shimeng Yu
{"title":"Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond","authors":"Xiaochen Peng, W. Chakraborty, Ankit Kaul, Wonbo Shim, M. Bakir, S. Datta, Shimeng Yu","doi":"10.1109/IEDM13553.2020.9372091","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372091","url":null,"abstract":"This paper presents 3D NeuroSim, a benchmark framework of monolithic 3D (M3D) integrated compute-in-memory (CIM) accelerators. To address the challenges of analog-to-digital converter (ADC) overhead and scaling limitations caused by high write voltage in emerging nonvolatile memory (eNVM), we propose partitioning the circuit modules in hybrid technology nodes across two stacked tiers with massive inter-tier vias. This framework features versatile back-end-of-line (BEOL)-compatible transistors, including laser-recrystallized silicon transistor and oxide transistor, and analyzes the thermal profile for M3D integration. Finally, we benchmark the CIM accelerators for VGG-8 on CIFAR-10 and reveal the substantial benefits in energy efficiency of a hybrid M3D architecture (45nm eNVM array+7nm ADC and logic).","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Butaud, S. Ballandras, M. Bousquet, A. Drouin, B. Tavel, I. Huyet, A. Clairet, I. Bertrand, A. Ghorbel, A. Reinhardt
{"title":"Innovative Smart Cut™ Piezo On Insulator (POI) Substrates for 5G acoustic filters","authors":"E. Butaud, S. Ballandras, M. Bousquet, A. Drouin, B. Tavel, I. Huyet, A. Clairet, I. Bertrand, A. Ghorbel, A. Reinhardt","doi":"10.1109/IEDM13553.2020.9372020","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372020","url":null,"abstract":"5G standards implementation drive significant challenges at the acoustic filter level and requires innovative solutions. A promising approach relies in Surface Acoustic Waves technology combined with a thin LiTaO3 piezoelectric crystal layer bonded on Silicon substrate – so called POI-substrate, but suffers from volume manufacturing solution. We will report how Smart Cut™ layer transfer technology enables it.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. King, J. Plombon, J. Bielefeld, J. Blackwell, S. Vyas, R. Chebiam, C. Naylor, D. Michalak, M. Kobrinsky, F. Gstrein, M. Metz, J. Clarke, R. Thapa, M. Paquette, V. Vemuri, N. Strandwitz, Y. Fan, M. Orlowski
{"title":"A Selectively Colorful yet Chilly Perspective on the Highs and Lows of Dielectric Materials for CMOS Nanoelectronics","authors":"S. King, J. Plombon, J. Bielefeld, J. Blackwell, S. Vyas, R. Chebiam, C. Naylor, D. Michalak, M. Kobrinsky, F. Gstrein, M. Metz, J. Clarke, R. Thapa, M. Paquette, V. Vemuri, N. Strandwitz, Y. Fan, M. Orlowski","doi":"10.1109/IEDM13553.2020.9371942","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371942","url":null,"abstract":"The remarkable advancement of CMOS electronics over the past two decades has been greatly aided by innovations allowing dielectric scaling across both ends of the permittivity spectrum. This paper describes how new dielectric innovations beyond permittivity scaling will allow both the extension of Moore’s law for another decade and usher in an array of new devices and computational paradigms.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134216431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Zhou, J. Ocker, A. Padovani, M. Pešić, M. Trentzsch, S. Dünkel, H. Mulaosmanovic, S. Slesazeck, L. Larcher, S. Beyer, S. Müller, T. Mikolajick
{"title":"Application and Benefits of Target Programming Algorithms for Ferroelectric HfO2 Transistors","authors":"H. Zhou, J. Ocker, A. Padovani, M. Pešić, M. Trentzsch, S. Dünkel, H. Mulaosmanovic, S. Slesazeck, L. Larcher, S. Beyer, S. Müller, T. Mikolajick","doi":"10.1109/IEDM13553.2020.9371975","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371975","url":null,"abstract":"The ferroelectric HfO2 based field effect transistor (FeFET) has been under research for many years and shows unique properties for applications in the field of emerging memories and in-memory computing. This work for the first time demonstrates how a target programming algorithm can improve the FeFET device characteristics with respect to endurance performance and variability for small device geometries. With this technique the threshold voltage Vt of the memory cell can be targeted to any desired value, which is essential for multilevel cells and analog in-memory computing as used in AI accelerators. The switching, trapping and detrapping characteristics of the cell and their influence on the target programming algorithm are presented. The trapping and leakage characteristics are modelled using the GinestraTM simulation software to extract the trap distribution in ferroelectric HfO2. Finally, a model for the underlying mechanism of the endurance degradation is proposed.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124337649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"0.5T0.5R - Introducing an Ultra-Compact Memory Cell Enabled by Shared Graphene Edge-Contact and h-BN Insulator","authors":"C. Yeh, Dujiao Zhang, W. Cao, K. Banerjee","doi":"10.1109/IEDM13553.2020.9371902","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371902","url":null,"abstract":"In this work, we experimentally demonstrate, in a manufacture-friendly process, a hybrid memory device to replace the traditional 1T1R memory unit that is composed of one-transistor and one-resistive-random-access-memory (RRAM), i.e., two separate devices. This novel device, which can be considered as a 0.5T0.5R memory cell, is structurally enabled by utilizing the unique graphene edge-contact and resistively switchable hexagonal boron nitride (h-BN) insulator. Aided by design optimization, record performance (<10 ns switching-speed), energy- (~0.07 pJ/bit) and area- efficiency (smallest footprint among all reported 2D RRAM memory units), as well as great retention (106 s) and endurance (>1000), have been achieved by this 0.5T0.5R memory cell. Moreover, the observed cell-resistance’s fine-tunability with ultrashort pulse count, pulse amplitude, and gate voltage uncovers the potential of this device for neuromorphic and in-memory computing.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127744048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Barraud, M. Ezzadeen, D. Bosch, T. Dubreuil, N. Castellani, V. Meli, J. Hartmann, M. Mouhdach, B. Previtali, B. Giraud, J. Noël, G. Molas, J. Portal, E. Nowak, F. Andrieu
{"title":"3D RRAMs with Gate-All-Around Stacked Nanosheet Transistors for In-Memory-Computing","authors":"S. Barraud, M. Ezzadeen, D. Bosch, T. Dubreuil, N. Castellani, V. Meli, J. Hartmann, M. Mouhdach, B. Previtali, B. Giraud, J. Noël, G. Molas, J. Portal, E. Nowak, F. Andrieu","doi":"10.1109/IEDM13553.2020.9371982","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371982","url":null,"abstract":"This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO2-based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F2/N is achieved (‘N’ being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 104 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121466401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Asselberghs, Q. Smets, T. Schram, B. Groven, D. Verreck, A. Afzalian, G. Arutchelvan, A. Gaur, D. Cott, T. Maurice, S. Brems, K. Kennes, A. Phommahaxay, E. Dupuy, D. Radisic, J. de Marneffe, A. Thiam, W. Li, K. Devriendt, C. Huyghebaert, D. Lin, M. Caymax, P. Morin, I. Radu
{"title":"Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab","authors":"I. Asselberghs, Q. Smets, T. Schram, B. Groven, D. Verreck, A. Afzalian, G. Arutchelvan, A. Gaur, D. Cott, T. Maurice, S. Brems, K. Kennes, A. Phommahaxay, E. Dupuy, D. Radisic, J. de Marneffe, A. Thiam, W. Li, K. Devriendt, C. Huyghebaert, D. Lin, M. Caymax, P. Morin, I. Radu","doi":"10.1109/IEDM13553.2020.9371926","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371926","url":null,"abstract":"Double gated WS2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of VT variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129194706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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