0.5T0.5R - Introducing an Ultra-Compact Memory Cell Enabled by Shared Graphene Edge-Contact and h-BN Insulator

Abstract

In this work, we experimentally demonstrate, in a manufacture-friendly process, a hybrid memory device to replace the traditional 1T1R memory unit that is composed of one-transistor and one-resistive-random-access-memory (RRAM), i.e., two separate devices. This novel device, which can be considered as a 0.5T0.5R memory cell, is structurally enabled by utilizing the unique graphene edge-contact and resistively switchable hexagonal boron nitride (h-BN) insulator. Aided by design optimization, record performance (<10 ns switching-speed), energy- (~0.07 pJ/bit) and area- efficiency (smallest footprint among all reported 2D RRAM memory units), as well as great retention (106 s) and endurance (>1000), have been achieved by this 0.5T0.5R memory cell. Moreover, the observed cell-resistance’s fine-tunability with ultrashort pulse count, pulse amplitude, and gate voltage uncovers the potential of this device for neuromorphic and in-memory computing.