H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang
{"title":"Millimeter-Wave Band CMOS RF Phased-Array Transceiver IC Designs for 5G Applications","authors":"H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang","doi":"10.1109/IEDM13553.2020.9371948","DOIUrl":null,"url":null,"abstract":"This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, POUT, stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows POUT/Ch. of >6.0dBm at EVM of -34dB (800MHz) and PDC/Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and PDC/Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of <-113dBm/100MHz in the 5G NR base-station system.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"35 15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9371948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, POUT, stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows POUT/Ch. of >6.0dBm at EVM of -34dB (800MHz) and PDC/Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and PDC/Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of <-113dBm/100MHz in the 5G NR base-station system.