I. Asselberghs, Q. Smets, T. Schram, B. Groven, D. Verreck, A. Afzalian, G. Arutchelvan, A. Gaur, D. Cott, T. Maurice, S. Brems, K. Kennes, A. Phommahaxay, E. Dupuy, D. Radisic, J. de Marneffe, A. Thiam, W. Li, K. Devriendt, C. Huyghebaert, D. Lin, M. Caymax, P. Morin, I. Radu
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引用次数: 17
Abstract
Double gated WS2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of VT variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.
在300mm Si CMOS晶圆厂中制备了栅极长度低至18nm的双门控WS2晶体管。通过使用大型统计数据集和完整300mm晶圆上的均匀性映射，我们构建了一个集成车辆，可以了解每个工艺步骤的影响并相应地开发，以提高设备性能。对VT变异性的深入分析表明，在不同的长度尺度上有多种可能的来源，其中最突出的是河道物质。这里展示的工作为二维材料的工业应用铺平了道路。
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