2015 IEEE 21st International On-Line Testing Symposium (IOLTS)最新文献

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Bayesian network early reliability evaluation analysis for both permanent and transient faults 永久故障和暂态故障的贝叶斯网络早期可靠性评估分析
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229819
Alessandro Vallero, A. Savino, Sotiris Tselonis, N. Foutris, Manolis Kaliorakis, G. Politano, D. Gizopoulos, S. Carlo
{"title":"Bayesian network early reliability evaluation analysis for both permanent and transient faults","authors":"Alessandro Vallero, A. Savino, Sotiris Tselonis, N. Foutris, Manolis Kaliorakis, G. Politano, D. Gizopoulos, S. Carlo","doi":"10.1109/IOLTS.2015.7229819","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229819","url":null,"abstract":"Analyzing the impact of software execution on the reliability of a complex digital system is an increasing challenging task. Current approaches mainly rely on time consuming fault injections experiments that prevent their usage in the early stage of the design process, when fast estimations are required in order to take design decisions. To cope with these limitations, this paper proposes a statistical reliability analysis model based on Bayesian Networks. The proposed approach is able to estimate system reliability considering both the hardware and the software layer of a system, in presence of hardware transient and permanent faults. In fact, when digital system reliability is under analysis, hardware resources of the processor and instructions of program traces are employed to build a Bayesian Network. Finally, the probability of input errors to alter both the correct behavior of the system and the output of the program is computed. According to experimental results presented in this paper, it can be stated that Bayesian Network model is able to provide accurate reliability estimations in a very short period of time. As a consequence it can be a valid alternative to fault injection, especially in the early stage of the design.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simplification of fully delay testable combinational circuits 全延迟可测试组合电路的简化
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229829
A. Matrosova, E. Mitrofanov, Toral Shah
{"title":"Simplification of fully delay testable combinational circuits","authors":"A. Matrosova, E. Mitrofanov, Toral Shah","doi":"10.1109/IOLTS.2015.7229829","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229829","url":null,"abstract":"Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-AND-XOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. They have a polynomial complexity. Experimental results demonstrate essential simplification of suggested circuits in contrast to fully delay testable circuits obtained by covering each ROBDD node with only Invert-AND-XOR sub-circuit.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses SRAM单元的激光故障注入:皮秒脉冲与纳秒脉冲
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229820
Marc Lacruche, N. Borrel, C. Champeix, Cyril Roscian, A. Sarafianos, J. Rigaud, J. Dutertre, E. Kussener
{"title":"Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses","authors":"Marc Lacruche, N. Borrel, C. Champeix, Cyril Roscian, A. Sarafianos, J. Rigaud, J. Dutertre, E. Kussener","doi":"10.1109/IOLTS.2015.7229820","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229820","url":null,"abstract":"Laser fault injection into SRAM cells is a widely used technique to perform fault attacks. In previous works, Roscian and Sarafianos studied the relations between the layout of the cell, its different laser-sensitive areas and their associated fault model using 50 ns duration laser pulses. In this paper, we report similar experiments carried out using shorter laser pulses (30 ps duration instead of 50 ns). Laser-sensitive areas that did not appear at 50 ns were observed. Additionally, these experiments confirmed the validity of the bit-set/bit-reset fault model over the bit-flip one. We also propose an upgrade of the simulation model they used to take into account laser pulses in the picosecond range. Finally, we performed additional laser fault injection experiments on the RAM memory of a microcontroller to validate the previous results.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip MUGEN:一种针对不可靠片上网络的高性能容错路由算法
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229835
A. Charif, N. Zergainoh, M. Nicolaidis
{"title":"MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip","authors":"A. Charif, N. Zergainoh, M. Nicolaidis","doi":"10.1109/IOLTS.2015.7229835","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229835","url":null,"abstract":"NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to increase the reliability and performance of NoCs. We combine these techniques to build a fault-tolerant, deadlock-free and congestion-aware routing algorithm called MUGEN. The algorithm comprises an optimized method to exchange messages between different virtual channel classes, a selection function that uses distant router link information to avoid dead-ends and a new congestion metric used to guide routing decisions towards less congested areas. We simulate an 8×8 Mesh NoC with fault injection to evaluate each method used by MUGEN individually before comparing the full algorithm with existing works from literature. We present promising results about the proposed techniques both in terms of fault-tolerance and performance.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126809457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Mining simulation metrics for failure triage in regression testing 为回归测试中的故障分类挖掘模拟度量
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229856
Zissis Poulos, A. Veneris
{"title":"Mining simulation metrics for failure triage in regression testing","authors":"Zissis Poulos, A. Veneris","doi":"10.1109/IOLTS.2015.7229856","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229856","url":null,"abstract":"Design debugging poses a major bottleneck in modern VLSI CAD flows, consuming up to 60% of the verification cycle. The debug pain, however, worsens in regression verification flows at the pre-silicon stage where myriads of failures can be exposed. These failures need to be properly grouped and distributed among engineers for further analysis before the next regression run commences. This high-level and complex debug problem is referred to as failure triage and largely remains a manual task in the industry. In this paper, we propose an automated failure triage flow that mines information from both failing and passing tests during regression, and automatically performs a coarse-grain partitioning of the failures. The proposed framework combines formal tools and novel statistical metrics to quantify the likelihood of specific design components being the root-cause of the observed failures. These components are then used to represent failures as high-dimensional objects, which are grouped by applying data-mining clustering algorithms. Finally, the generated failure clusters are automatically prioritized and passed to the best suited engineers for detailed analysis. Experimental results show that the proposed approach groups related failures together with 90% accuracy on the average, and efficiently prioritizes the responsible design errors for 86% of the exposed failures.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115390049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An effective embedded test & diagnosis solution for external memories 一个有效的嵌入式测试和诊断解决方案的外部存储器
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229852
Gurgen Harutunyan, Y. Zorian
{"title":"An effective embedded test & diagnosis solution for external memories","authors":"Gurgen Harutunyan, Y. Zorian","doi":"10.1109/IOLTS.2015.7229852","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229852","url":null,"abstract":"From a structural viewpoint, an external memory linked to a system-on-chip (SoC) via high speed I/Os is typically composed of one or more memory dies/chips that interact with SoC using high bandwidth. Though testing an external memory and its high speed interconnects has always been a challenge, nevertheless this challenge became more critical with the increased use of high density packages, such as 2.5D or 3D. Not only fault detection but also fault diagnosis is important for fault type and fault location identification in external memories. In this paper an effective embedded test and diagnosis solution for external memory array and interconnects is proposed. The paper presents a new taxonomy for fault classification and new fault detection and diagnosis algorithm identifying external memory fault types and their locations. Finally it describes a built-in self- test (BIST) implementation which was successfully applied to DDR4 SDRAM.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124925389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Soft error immune latch under SEU related double-node charge collection 双节点电荷收集下的软误差免疫锁存
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229830
K. Katsarou, Y. Tsiatouhas
{"title":"Soft error immune latch under SEU related double-node charge collection","authors":"K. Katsarou, Y. Tsiatouhas","doi":"10.1109/IOLTS.2015.7229830","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229830","url":null,"abstract":"The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double node charge sharing. Simulations results and comparisons on a variety of SEU tolerant techniques are presented to evaluate the efficiency of the proposed latch.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129922512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the maximization of the sustained switching activity in a processor 关于处理器中持续切换活动的最大化
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229826
R. Cantoro, M. Reorda, Alireza Rohani, H. Kerkhoff
{"title":"On the maximization of the sustained switching activity in a processor","authors":"R. Cantoro, M. Reorda, Alireza Rohani, H. Kerkhoff","doi":"10.1109/IOLTS.2015.7229826","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229826","url":null,"abstract":"Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127434852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The future of fault tolerant computing 容错计算的未来
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229841
J. Abraham, R. Iyer, D. Gizopoulos, D. Alexandrescu, Y. Zorian
{"title":"The future of fault tolerant computing","authors":"J. Abraham, R. Iyer, D. Gizopoulos, D. Alexandrescu, Y. Zorian","doi":"10.1109/IOLTS.2015.7229841","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229841","url":null,"abstract":"Fault tolerant (or dependable) computing has always been an exciting research area in the intersection of computer science and engineering and electrical and electronics engineering. During the last two decades the applicability of the methods and tools that the fault tolerance research community produces has expanded to virtually all application domains. The type of fault tolerance methods employed in a computing system depend on: (a) the faults expected to affect the system, (b) the importance of errors in the system operation, (c) the design, cost and power budgets that can allocated to fault tolerance and reliable operation. New solutions and tools in fault tolerant computing are emerging to deal with the very broad spectrum of values that all (a), (b) and (c) can take in today's computing landscape.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"43 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Towards Trojan circuit detection with maximum state transition exploration 基于最大状态转移探索的木马电路检测
2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229831
Joseph Lenox, S. Tragoudas
{"title":"Towards Trojan circuit detection with maximum state transition exploration","authors":"Joseph Lenox, S. Tragoudas","doi":"10.1109/IOLTS.2015.7229831","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229831","url":null,"abstract":"An approach for Trojan circuit detection in a finite state machine is presented. It is based on a model where long sequences of inputs that are applied to the system in the functional mode can detect if Trojan hardware is triggered with high probability. An efficient and scalable input generation algorithm for broadside tests is introduced.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122650948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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