2015 IEEE 21st International On-Line Testing Symposium (IOLTS)最新文献

An accurate soft error propagation analysis technique considering temporal masking disablement 一种考虑时间掩蔽抑制的精确软误差传播分析技术

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229822

Y. Kimi, Go Matsukawa, Shuhei Yoshida, S. Izumi, H. Kawaguchi, M. Yoshimoto

引用次数: 4

Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis 基于灵敏度分析的SRAM fpga上SEU仿真优化

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229827

Anis Souari, C. Thibeault, Y. Blaquière, R. Velazco

引用次数: 2

Adaptive healing procedure for lifetime improvement in Wireless Sensor Networks 无线传感器网络寿命改善的自适应修复程序

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229833

Diane Tchuani Tchakonte, E. Simeu, M. Tchuenté

引用次数: 2

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture 混合容错体系结构的设计空间探索与优化

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229838

I. Wali, A. Virazel, A. Bosio, P. Girard, M. Reorda

引用次数: 7

Efficient observation point selection for aging monitoring 有效的老化监测观测点选择

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229855

Chang Liu, M. Kochte, H. Wunderlich

引用次数: 12

Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit 超大面积集成电路中嵌入式现场可编程互连网络的缺陷诊断算法

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229837

Gontran Sion, Y. Blaquière, Y. Savaria

引用次数: 4

A single chip dependable and adaptable payload Data Processing Unit 单片可靠、适应性强的有效载荷数据处理单元

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229847

N. Kranitis, A. Tsigkanos, G. Theodorou, Ioannis Sideris, A. Paschalis

{"title":"A single chip dependable and adaptable payload Data Processing Unit","authors":"N. Kranitis, A. Tsigkanos, G. Theodorou, Ioannis Sideris, A. Paschalis","doi":"10.1109/IOLTS.2015.7229847","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229847","url":null,"abstract":"The current state-of-the-art space-grade reconfigurable SRAM FPGAs provide unprecedented levels of integration and performance and advanced features previously available only to commercial developers such as dynamic partial reconfiguration. On-board payload data processing based on an adaptable SRAM FPGA based hardware platform offers unique advantages over both one-time programmable anti-fuse FPGAs and ASICs, enabling an adaptable instrument with significant savings in mass, power, cost, resources and flexibility. In this paper, for the first time, we integrate the instrument system supervisor processor along with dedicated, adaptable and high-performance on-board data processing functions in a single-chip, dependable and adaptable payload Data Processing Unit (DPU), based on the space-grade Xilinx Virtex-5QV FPGA. The introduced single-chip DPU supports self-configuration management without the requirement of an external configurator/scrubber. Furthermore, a system-level SEE mitigation strategy is proposed that employs EDAC, TMR and internal scrubbing to guarantee total immunity under extremely harsh radiation environments. The functionality of the proposed single-chip DPU is validated using a hardware demonstrator platform that hosts the commercial equivalent (XC5VFX130T) of the space-grade Xilinx Virtex-5QV FPGA.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"152 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Timing-resilient Network-on-Chip architectures 时序弹性的片上网络架构

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229836

Alexandros Panteloukas, Anastasios Psarras, C. Nicopoulos, G. Dimitrakopoulos

{"title":"Timing-resilient Network-on-Chip architectures","authors":"Alexandros Panteloukas, Anastasios Psarras, C. Nicopoulos, G. Dimitrakopoulos","doi":"10.1109/IOLTS.2015.7229836","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229836","url":null,"abstract":"Networks-on-Chip (NoC) have been established as the de facto standard for on-chip communication in multi-/many-core systems, due to their innate scalability properties pertaining to performance and physical implementation. Spanning the entire chip, the NoC suffers from both inter-die and intra-die variations. In addition to static variability, the NoC is also afflected by dynamic variations, such as fast VDD droops, temperature, and aging effects. Such variations cause unpredictable behavior in the timing characteristics of the NoC components, which need significant timing margins to ensure always-correct operation. Consequently, the potential for high-frequency operation is impeded. In this paper, we propose a timing-error-resilient mechanism called TRNoC, which allows the NoC to operate at higher frequencies, at the expense of sporadically experiencing run-time timing errors, which are handled by an error recovery strategy. TRNoC includes a lightweight timing-error detection mechanism, together with a distributed error recovery mechanism, which allow for lossless operation, while leaving the error-free parts of the network unaffected. Hardware implementation results demonstrate the efficiency of TRNoC and its potential as a scalable timing-error-resilient NoC architecture.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131068753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Characterizing fault propagation in safety-critical processor designs 安全关键处理器设计中的故障传播特征

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229848

Jaime Espinosa, Carles Hernández, J. Abella

引用次数: 7

Reliability/yield trade-off in mitigating “no trouble found” field returns 可靠性与产量之间的权衡，以减少“无故障”的现场退货

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229854

A. Haggag, N. Sumikawa, Aamer Shaukat

引用次数: 6