Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit

Abstract

Algorithms are proposed to diagnose defects in a defect tolerant field programmable interconnection network embedded in a large area integrated circuit. The proposed diagnosis algorithms use a diagonal configuration approach to reduce the cone of influence of individual tests, thus allowing parallel tests according to diagonal patterns. The proposed algorithms avoid redundant diagnosis tests. Efficiency of the proposed diagnosis algorithms are calculated in terms of the number of cycles of a JTAG FSM required to apply the test. Results show a 113-fold test time reduction in the considered interconnection network.