2015 IEEE 21st International On-Line Testing Symposium (IOLTS)最新文献_第2页

Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors 芯片多处理器中按需SBST下的有效检查点和回滚

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229842

M. Skitsas, C. Nicopoulos, M. Michael

{"title":"Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors","authors":"M. Skitsas, C. Nicopoulos, M. Michael","doi":"10.1109/IOLTS.2015.7229842","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229842","url":null,"abstract":"In-field on-line testing techniques have recently been proposed for permanent fault detection caused by wear-out/aging-related defects manifesting during the lifetime of a system. Selective Software-Based Self-Testing (SBST) is one such paradigm focusing primarily on the recently stressed functional units of a multicore system at a sub-core granularity, in an attempt to reduce the application performance penalty caused by periodically testing the entire system. In this work, we complement our O/S-enabled framework DeamonGuard for on-demand (selective) SBST to support fault recovery capabilities. Towards this goal, we propose an efficient check pointing and rollback recovery mechanism which, upon fault detection, can restore the system to the most recently valid correct state and resume the normal operation assuming disabling of the faulty core, thereby leading to a healthy (but degraded) system. The work in this paper concentrates on reducing the number of stored checkpoints required when testing at a sub-core granularity, and minimizing the recovery penalty of such framework. We evaluate and demonstrate the overhead of the proposed recovery mechanism, and our results indicate a practical reduction in the number of stored checkpoints as well as a significant improvement in recovery latency for the cases where the faults are correlated with the stressed units.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127525816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Real-time on-chip supply voltage sensor and its application to trace-based timing error localization 实时片上电源电压传感器及其在基于跟踪的定时误差定位中的应用

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229857

Miho Ueno, M. Hashimoto, T. Onoye

引用次数: 12

Fault-tolerant system for catastrophic faults in AMR sensors AMR传感器灾难性故障容错系统研究

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229834

Andreina Zambrano, H. Kerkhoff

{"title":"Fault-tolerant system for catastrophic faults in AMR sensors","authors":"Andreina Zambrano, H. Kerkhoff","doi":"10.1109/IOLTS.2015.7229834","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229834","url":null,"abstract":"Anisotropic Magnetoresistance angle sensors are widely used in automotive applications considered to be safety-critical applications. Therefore dependability is an important requirement and fault-tolerant strategies must be used to guarantee the correct operation of the sensors even in case of failures. AMR sensors are configured with two Wheatstones bridges where catastrophic (hard) as well as parametric faults can ocurr. Catastrophic faults are mainly related to the conditions of the bridge resistances. If a hard fault occurs at any of the resistances, the sensor must be taken out of operation because the angle can not longer be reliably computed. Previous proposed fault-tolerant systems are based on physical redundancy with hardware duplication, which usually implies higher production cost and can be restricted by the mechanical construction of the sensor. However the proposed fault-tolerant system is based on analytical redundancy to obtain the required voltages to calculate the angle. Results indicate the fault-tolerant system can handle catastrophic fault at any of the bridge resistances, which is especially useful in safety-critical applications. Future research will be focused on parametric faults.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123340491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Failure mitigation in linear, sesquilinear and bijective operations on integer data streams via numerical entanglement 基于数值纠缠的整数数据流线性、半线性和双目标操作的故障缓解

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229844

M. A. Anam, Y. Andreopoulos

{"title":"Failure mitigation in linear, sesquilinear and bijective operations on integer data streams via numerical entanglement","authors":"M. A. Anam, Y. Andreopoulos","doi":"10.1109/IOLTS.2015.7229844","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229844","url":null,"abstract":"A new roll-forward technique is proposed that recovers from any single fail-stop failure in M integer data streams (M ≥ 3) when undergoing linear, sesquilinear or bijective (LSB) operations, such as: scaling, additions/subtractions, inner or outer vector products and permutations. In the proposed approach, the M input integer data streams are linearly superimposed to form M numerically entangled integer data streams that are stored inplace of the original inputs. A series of LSB operations can then be performed directly using these entangled data streams. The output results can be extracted from any M-1 entangled output streams by additions and arithmetic shifts, thereby guaranteeing robustness to a fail-stop failure in any single stream computation. Importantly, unlike other methods, the number of operations required for the entanglement, extraction and recovery of the results is linearly related to the number of the inputs and does not depend on the complexity of the performed LSB operations. We have validated our proposal in an Intel processor (Haswell architecture with AVX2 support) via convolution operations. Our analysis and experiments reveal that the proposed approach incurs only 1.8% to 2.8% reduction in processing throughput in comparison to the failure-intolerant approach. This overhead is 9 to 14 times smaller than that of the equivalent checksum-based method. Thus, our proposal can be used in distributed systems and unreliable processor hardware, or safety-critical applications, where robustness against fail-stop failures becomes a necessity.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Workload characterization and prediction: A pathway to reliable multi-core systems 工作负载表征和预测:通往可靠多核系统的途径

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229843

Monir Zaman, A. Ahmadi, Y. Makris

{"title":"Workload characterization and prediction: A pathway to reliable multi-core systems","authors":"Monir Zaman, A. Ahmadi, Y. Makris","doi":"10.1109/IOLTS.2015.7229843","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229843","url":null,"abstract":"As a result of technology scaling, power density of multi-core chips increases and leads to temperature hot-spots which accelerate device aging and chip failure. Moreover, intense efforts to reduce power consumption by employing low-power techniques decrease the reliability of new design generations. Traditionally, reactive thermal/power management techniques have been used to take appropriate action when the temperature reaches a threshold. However, these approaches do not always balance temperature and, as a result, may degrade system reliability. Therefore, to distribute temperature evenly across all cores, a proactive mechanism is needed to forecast future workload characteristics and the corresponding temperature, in order to make decisions before hot spots occur. Such proactive methods rely on an engine to precisely predict future workload characteristics. In this work, we first discuss the state-of-the-art methods for predicting workload dynamics and we compare their performance. We, then, introduce a prediction method based on Support Vector Regression (SVR), which accurately predicts the workload behavior several steps ahead. To evaluate the effectiveness of our approach, we use several programs from the PARSEC benchmark suite on an UltraSPARC T1 processor running the Sun Solaris operating system and we extract architectural traces. Then, the extracted traces are used to generate power and thermal profiles for each core using the McPAT and Hot-Spot simulators. Our results show that the proposed method forecasts workload dynamics and power very accurately and outperforms previous prediction techniques.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129965239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Fault modeling and testing of through silicon via interconnections 通硅互连故障建模与测试

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229824

V. Gerakis, Leonidas Katselas, A. Hatzopoulos

引用次数: 1

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients 单事件瞬变下设计脆弱性的高效多级形式化分析与估计

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229818

Ghaith Bany Hamad, O. Mohamed, Y. Savaria

引用次数: 6

Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF) 通过最小化时间脆弱性因子(TVF)来减少触发器SEU

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229851

A. Evans, Enrico Costenaro, A. Bramnik

引用次数: 4

New byte error correcting codes with simple decoding for reliable cache design 新的字节纠错码与简单的解码可靠的缓存设计

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229859

Lake Bu, M. Karpovsky, Zhen Wang

引用次数: 4

A call for cross-layer and cross-domain reliability analysis and management 要求进行跨层、跨域的可靠性分析与管理

2015 IEEE 21st International On-Line Testing Symposium (IOLTS) Pub Date : 2015-07-06 DOI: 10.1109/IOLTS.2015.7229821

D. Alexandrescu, A. Evans, Enrico Costenaro, M. Glorieux

{"title":"A call for cross-layer and cross-domain reliability analysis and management","authors":"D. Alexandrescu, A. Evans, Enrico Costenaro, M. Glorieux","doi":"10.1109/IOLTS.2015.7229821","DOIUrl":"https://doi.org/10.1109/IOLTS.2015.7229821","url":null,"abstract":"For many applications, reliability, availability and trustability are key factors, requiring careful design to meet the end users expectations. The complex ASICs, which are now ubiquitous, often embed tens of millions of flip-flops, hundreds of megabits of embedded SRAM, and hundreds of millions of combinatorial cells. These designs integrate IP from multiple providers and are implemented in advanced process technologies, making it challenging to evaluate their reliability. Initiatives such as RIIF (Reliability Information Interchange Format) allow the formalization, specification and modeling of extra-functional, reliability properties for technology, circuits and systems. Continuing these efforts, we propose RAFT (Reliability Architect Framework and Toolset) - a reliability-centric framework including reliability data and models, methodologies and tools allowing system reliability exploration and optimization using mathematical models and high-level tools. The proposed approach can be combined with performance management methodologies aiming at reducing the engineering effort devoted to reliability analysis and improvement.","PeriodicalId":413023,"journal":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129466199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0