Fault modeling and testing of through silicon via interconnections

Abstract

The case of a defected TSV that has been cracked at the point where an impurity or a void hole originally had been is analyzed in this study. A lumped analytical electrical circuit that models the behavior of this defect is proposed. TSV fault modeling offers assistance in developing new test methods that would improve the reliability of the 3D ICs. The structure is simulated using a commercial 3D resistance, capacitance and inductance extraction tool. A test method that determines the possible characteristics of the defect is presented.