基于灵敏度分析的SRAM fpga上SEU仿真优化

Anis Souari, C. Thibeault, Y. Blaquière, R. Velazco
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引用次数: 2

摘要

本文提出了一种新的、高效的基于Xilinx sram的fpga电路单事件扰动灵敏度估计的故障注入方法。该方法根据特定配置位子集的内容和所配置的FPGA资源类型对故障注入进行优先级排序。新方法还可以最大限度地提高注入过程中翻转的临界比特数或临界比特数的估计精度。结果表明,该方法比传统的随机故障注入方法速度提高了2个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis
This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.
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