Soft error immune latch under SEU related double-node charge collection

Abstract

The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double node charge sharing. Simulations results and comparisons on a variety of SEU tolerant techniques are presented to evaluate the efficiency of the proposed latch.