An effective embedded test & diagnosis solution for external memories

Abstract

From a structural viewpoint, an external memory linked to a system-on-chip (SoC) via high speed I/Os is typically composed of one or more memory dies/chips that interact with SoC using high bandwidth. Though testing an external memory and its high speed interconnects has always been a challenge, nevertheless this challenge became more critical with the increased use of high density packages, such as 2.5D or 3D. Not only fault detection but also fault diagnosis is important for fault type and fault location identification in external memories. In this paper an effective embedded test and diagnosis solution for external memory array and interconnects is proposed. The paper presents a new taxonomy for fault classification and new fault detection and diagnosis algorithm identifying external memory fault types and their locations. Finally it describes a built-in self- test (BIST) implementation which was successfully applied to DDR4 SDRAM.