Mining simulation metrics for failure triage in regression testing

Zissis Poulos, A. Veneris
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引用次数: 1

Abstract

Design debugging poses a major bottleneck in modern VLSI CAD flows, consuming up to 60% of the verification cycle. The debug pain, however, worsens in regression verification flows at the pre-silicon stage where myriads of failures can be exposed. These failures need to be properly grouped and distributed among engineers for further analysis before the next regression run commences. This high-level and complex debug problem is referred to as failure triage and largely remains a manual task in the industry. In this paper, we propose an automated failure triage flow that mines information from both failing and passing tests during regression, and automatically performs a coarse-grain partitioning of the failures. The proposed framework combines formal tools and novel statistical metrics to quantify the likelihood of specific design components being the root-cause of the observed failures. These components are then used to represent failures as high-dimensional objects, which are grouped by applying data-mining clustering algorithms. Finally, the generated failure clusters are automatically prioritized and passed to the best suited engineers for detailed analysis. Experimental results show that the proposed approach groups related failures together with 90% accuracy on the average, and efficiently prioritizes the responsible design errors for 86% of the exposed failures.
为回归测试中的故障分类挖掘模拟度量
设计调试是现代VLSI CAD流程的主要瓶颈,它消耗了高达60%的验证周期。然而,在预硅阶段的回归验证流中,调试的痛苦会加剧,在这个阶段可能会暴露出无数的故障。这些故障需要适当地分组,并在工程师之间进行分配,以便在下一个回归运行开始之前进行进一步分析。这种高级和复杂的调试问题被称为故障分类,并且在很大程度上仍然是行业中的手动任务。在本文中,我们提出了一个自动故障分类流,它在回归过程中从失败和通过的测试中挖掘信息,并自动执行故障的粗粒度划分。提出的框架结合了正式工具和新颖的统计度量来量化特定设计组件是观察到的故障的根本原因的可能性。然后使用这些组件将故障表示为高维对象,并通过应用数据挖掘聚类算法对其进行分组。最后,生成的故障集群自动按优先级排序,并传递给最适合的工程师进行详细分析。实验结果表明,该方法将相关故障分组在一起,平均准确率为90%,并对86%的暴露故障有效地优先考虑责任设计错误。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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